Cascode connected SiC-JFET with SiC-SBD and enhancement device
An apparatus that includes a first device connected to an inductor. The first device includes a first silicon carbide (SiC) junction gate field-effect transistor (JFET), a first SiC schottky barrier diode (SBD) connected to a gate and a drain of the first SiC JFET, and a first silicon (Si) transistor connected to transmit current to a source of the first SiC JFET. An inductor input terminal is connected to the drain of the first SiC JFET.
1. An apparatus comprising:
an inductor comprising an input terminal and an output terminal;
a first device comprising:
a first silicon carbide (SiC) junction gate field-effect transistor (JFET), and;
a first SiC schottky barrier diode (SBD) connected to a gate and a drain of the first SiC JFET;
a first silicon (Si) transistor connected to transmit current to a source of the first SiC JFET;
wherein the inductor input terminal is connected to the drain of the first SiC JFET.
2. The apparatus of claim 1 wherein the first SiC SBD is connected to transmit current when the first Si transistor is deactivated.
3. The apparatus of claim 2 wherein the inductor input terminal is connected to the SiC SBD.
4. The apparatus of claim 2 wherein the first SiC JFET and first SiC SBD are formed on a SiC die.
5. The apparatus of claim 4 wherein the first Si transistor is formed on a Si die, and wherein the SiC die and the Si die are separate dies.
6. The apparatus of claim 3 , wherein the first Si transistor comprises a first Si bipolar junction transistor (BJT).
7. The apparatus of claim 6 , wherein: the source of the first SiC JFET is connected to a collector of the first Si BJT, and wherein an anode of first SiC SBD is connected to the gate of the first SiC JFET and an emitter of the first Si BJT, and wherein a cathode of the first SiC SBD is connected to the drain of the first SiC JFET.
8. The apparatus of claim 3 :
wherein the first Si transistor comprises a first Si insulated-gate bipolar transistor (IGBT);
wherein the source of the first SiC JFET is connected to a collector of the first Si IGBT;
wherein an anode of first SiC SBD is connected to the gate of the first SiC JFET and an emitter of the first Si IGBT;
wherein a cathode of the first SiC SBD is connected to the drain of the first SiC JFET.
9. The apparatus of claim 3 further comprising:
a second device comprising:
a second SiC JFET;
a second Si transistor connected to a source of the second SiC;
wherein a gate of the second SiC JFET is connected to the input terminal of the inductor.
10. The apparatus of claim 9 wherein the second device further comprises a second SiC SBD connected between a gate and a drain of the second SiC JFET.
11. The apparatus of claim 10 :
wherein the first Si transistor comprises a first Si MOSFET;
wherein the second Si transistor comprises a second Si MOSFET;
wherein the cathode of first SiC SBD is connected to the gate of the second SiC JFET, a source of the second Si MOSFET, and the input terminal of the inductor.
12. The apparatus of claim 11 further comprising a circuit for generating non-overlapping, complementary first and second square waves for driving the gates of the first and second Si MOSFETs, respectively.
13. The apparatus of claim 12 ;
wherein the drain of the second SiC JFET is configured to be connected to a voltage source;
wherein the source of the first Si MOSFET is configured to be coupled to ground, and;
wherein the output terminal of the inductor is configured to provide current to a device.
14. The apparatus of claim 8 further comprising:
a second device comprising:
a second SiC JFET;
a second SiC SBD connected between a gate and a drain of the second SiC JFET;
a second Si BJT connected to transmit current to a source of the second SiC JFET;
wherein a gate of the second SiC JFET is connected to the input terminal of the inductor.
15. The apparatus of claim 14 further comprising:
a third device comprising:
a third SiC JFET;
a third SiC SBD connected between a gate and a drain of the third SiC JFET;
a third Si BJT connected to transmit current to a source of the third SiC JFET;
wherein a gate of the third SiC JFET is connected to the output terminal of the inductor;
a fourth device comprising:
a fourth SiC JFET;
a fourth SiC SBD connected between a gate and a drain of the fourth SiC JFET;
a fourth Si BJT connected to transmit current to a source of the fourth SiC JFET;
wherein a drain of the fourth SiC JFET is connected to the output terminal of the inductor.
16. An apparatus comprising:
a DC-DC converter comprising:
an inductor comprising an input terminal and an output terminal;
a first device comprising:
a first silicon carbide (SiC) junction gate field-effect transistor (JFET), and;
a first SiC schottky barrier diode (SBD) connected to a gate and a drain of the first SiC JFET;
a first silicon (Si) bipolar junction transistor (BJT) connected to transmit current to a source of the first SiC JFET;
wherein the inductor input terminal is connected to the drain of the first SiC JFET.
17. The apparatus of claim 16 wherein the first SiC SBD is connected to transmit current when the first Si BJT transistor is deactivated.
18. The apparatus of claim 16 wherein the inductor input terminal is connected to the SiC SBD.
19. An apparatus comprising:
an H-bridge comprising
an inductor comprising an input terminal and an output terminal;
a first device comprising:
a first silicon carbide (SiC) junction gate field-effect transistor (JFET), and;
a first SiC schottky barrier diode (SBD) connected to a gate and a drain of the first SiC JFET;
a first silicon (Si) bipolar junction transistor (BJT) connected to transmit current to a source of the first SiC JFET;
wherein the inductor input terminal is connected to the drain of the first SiC JFET.