Efficient and dependable clock synchronization in hardware

1. A method for synchronizing a number of clock pulses, the method comprising:

for each clock pulse, translating incoming clock signal transitions to a binary value encoding a deviation from an expected arrival time;

selecting a first binary value and a second binary value;

calculating an average of these values and computing its difference to the expected value; and

applying a corresponding phase correction or clock shift.

2. The method of claim 1 , further comprising the step of correcting a frequency of one or more of the pulse signals.

3. The method of claim 1 , characterized in that the incoming clock signal transitions are translated by a multiplexed time-to-digital converter (TDC).

4. The method of claim 1 , wherein ring-oscillator TDCs are used and wherein a control bit is used for indicating on which side of the oscillator ring the oscillator was halted by the incoming signal.

5. The method of claim 2 , wherein two relevant signals are selected before feeding the signals into the TDC, using a sorting network.

6. The method of claim 3 , wherein approximate frequency measurements are obtained from a single measurement of phase differences.

7. The method of claim 1 , wherein a node is accelerated if it observes fewer then n−f signals in a local time window.

8. Metastability-containing electronic circuit, usable for synchronizing a number of clock pulses, the circuit comprising:

inputs, constructed and adapted to receive one or more electrical input signals;

combinational logic constructed and adapted to generate one or more electrical output signals, based on the one or more input signals; and

outputs, constructed and adapted to output the one or more output signals;

wherein

the combinational logic generates at least one stable output signal ( 0 , 1 ), based on at least one combination of stable and metastable input signals ( 0 , 1 , M), and wherein

at least two input signals are clock pulses and at least one output signal represents a clock difference between the input signals, and wherein

the combinational logic encodes the clock difference in a binary reflected Gray code (BRCG).

9. The circuit according to claim 8 , wherein the combinational logic is a multiplexer.

10. The circuit according to claim 9 , wherein an AND gate checks whether the inputs are equal and feeds its result into an OR gate.

11. The circuit according to claim 8 , wherein a circuit sorting two B-bit gray code inputs with possibly one metastable bit each are obtained by using a recursive approach whose size and depth are O(b 2 ) and O(b) respectively.

12. The circuit according to claim 8 , wherein the combinational logic selects one of the input signals.

13. The circuit according to claim 8 , wherein at least one input signal is delayed and the combinational logic generates the output signals, based on the delayed input signal.

14. The circuit according to claim 8 , wherein the combinational logic is a sorting network.

15. The circuit according to claim 8 , further comprising a digitally controlled oscillator (DCO), controlled by at least one of the output signals.

16. Metastability-containing electronic circuit, usable for synchronizing a number of clock pulses, the circuit comprising:

inputs, constructed and adapted to receive one or more electrical input signals;

combinational logic constructed and adapted to generate one or more electrical output signals, based on the one or more input signals; and

outputs, constructed and adapted to output the one or more output signals, wherein

the combinational logic generates at least one stable output signal (0, 1), based on at least one combination of stable and metastable input signals (0, 1, M), and wherein

the circuit comprises a sorting circuit sorting two B-bit gray code inputs with possibly one metastable bit each, the sorting circuit obtained by using a recursive approach whose size and depth are O(b2) and O(b) respectively.

17. The circuit according to claim 16 , wherein the combinational logic comprises a multiplexer.

18. The circuit according to claim 16 , wherein at least one input signal is delayed and the combinational logic generates the output signals, based on the delayed input signal.

19. The circuit according to claim 16 , wherein the combinational logic comprises a sorting network.

20. The circuit according to claim 16 , further comprising a digitally controlled oscillator (DCO), controlled by at least one of the output signals.