IP Library Granted Patent US 12,730,174
Granted Patent B2
US 12,730,174 · App. 18/645,529 · Granted Sep 8, 2026

5-PS-resolution waveform-capture-device on a field-programmable gate-array with dynamic phase-shifting

Inventors: Noeloikeau Charlot (Columbus, OH); Daniel Gauthier (Columbus, OH); Andrew Pomerance (Alexandria, VA)
Assignee: Ohio State Innovation Foundation
G01R35/005G01R13/02G04F10/005H03K19/173
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Quick Facts
Patent No.
US 12,730,174
App. No.
18/645,529
Granted
Sep 8, 2026
Kind
B2
Abstract

A waveform capture device (WCD) is a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD may be implemented via modular code on an off-the-shelf field-programmable gate-array (FPGA) and incorporates both time-to-digital converter (TDC) and digital storage oscilloscope (DSO) functionality. The device captures a waveform by taking snapshots of a signal as it propagates down an ultra-fast transmission line known as a carry chain (CC). It may be calibrated via a dynamic phase-shifting (DPS) method that requires substantially less data and resources than conventional techniques.

Claims (23)

1 . A device comprising:

a clock that generates a clock signal;

a time-to-digital converter (TDC) that includes a carry chain (CC); and

a digital oscilloscope (DO),

wherein an input signal(S) passes through the carry chain (CC) in accordance with the clock signal.

2 . The device of claim 1 , wherein the device is a waveform-capture-device (WCD).

3 . The device of claim 2 , wherein the WCD is a 5 ps-resolution TDC/ultra-fast DO hybrid.

4 . The device of claim 2 , wherein the WCD is implemented on a field-programmable gate-array (FPGA).

5 . The device of claim 2 , wherein the WCD is configured to measure complex GHz frequency waveforms at picosecond time intervals.

6 . The device of claim 2 , wherein the CC captures a digital waveform without encoding the digital waveform.

7 . The device of claim 6 , wherein the CC includes at least one carry element (CE) and an adder to route the input signal(S) to a corresponding one of the registers.

8 . The device of claim 7 , wherein each CC is used to buffer an input signal and wherein the registers are used to capture a waveform of the input signal on an edge of a clock.

9 . The device of claim 8 , wherein the at least one CE passes the input signal to another CE after a time-delay.

10 . A waveform-capture-device (WCD) comprising:

a clock that generates a clock signal;

a time-to-digital converter (TDC);

a digital oscilloscope (DO); and

a tapped delay line (TDL) comprising a plurality of carry-chains (CCs) and a plurality of registers,

wherein an input signal(S) passes through the carry chain (CC) and buffered in the registers in accordance with the clock signal (C).

11 . The device of claim 10 , wherein the WCD is implemented on a field-programmable gate-array (FPGA), wherein the WCD is configured to measure complex GHz frequency waveforms at picosecond time intervals.

12 . The device of claim 10 , wherein each CC is used to buffer an input signal and wherein the registers are used to capture a waveform of the input signal on an edge of the clock signal, and wherein each CC comprises at least one carry-element (CD) that passes the input signal to another CE after a time-delay.

13 . The device of claim 12 , wherein the CCs are configured to capture a digital waveform without encoding the digital waveform.

14 . The device of claim 11 , wherein the DPS uses dynamic-phase calibration (DPC) and wherein the DPS functions by adjusting the phase of a stable on-board clock, wherein the clock is a phase-lock loop (PLL).

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2024
From: POMERANCE, ANDREW
To: POTOMAC RESEARCH LLC
Reel/Frame 068080/0716 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2024
From: CHARLOT, NOELOIKEAU; GAUTHIER, DANIEL
To: OHIO STATE INNOVATION FOUNDATION
Reel/Frame 068080/0600 →
Continuity (3)
Continuation 17676340 · Feb 21, 2022
Provisional Application 63177435 · Apr 21, 2021
Related Publication 20260023145A1 · Jan 22, 2026
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