Memory device and manufacturing method thereof
There are provided a memory device and a manufacturing method thereof. A method of manufacturing a memory device may include forming, on a substrate, a conductive layer, a sacrificial layer, and a stack structure. The method may include forming a plurality of vertical holes by etching a portion of the stack structure. The method may include forming a memory layer and a channel layer along internal surfaces of the vertical holes. The method may include forming a slit trench exposing a portion of the sacrificial layer therethrough by etching a portion of the stack structure between the vertical holes. The method may include exposing a portion of the channel layer and the first conductive layer through a lower portion of the stack structure by removing portions of the sacrificial layer and the memory layer. The method may include forming another conductive layer along surfaces of the exposed portion of the channel layer and the first conductive layer. The method may include forming a slit insulating layer in the slit trench.
1. A method of manufacturing a memory device, the method comprising:
forming, on a substrate, a first conductive layer, a second conductive layer, a sacrificial layer, and a stack structure;
forming a plurality of vertical holes by etching portions of the stack structure, the sacrificial layer and the second conductive layer;
forming a memory layer and a channel layer along internal surfaces of the vertical holes;
forming a slit trench exposing a portion of the sacrificial layer therethrough by etching a portion of the stack structure between the vertical holes;
exposing a portion of the channel layer and the second conductive layer through a lower portion of the stack structure by removing portions of the sacrificial layer and the memory layer;
forming a third conductive layer along surfaces of the exposed portion of the channel layer and the second conductive layer after exposing the portion of the channel layer and the second conductive layer; and
forming a slit insulating layer in the slit trench.
2. The method of claim 1 , wherein the second and third conductive layers and the channel layer are formed of the same material as one another.
3. The method of claim 2 , wherein the second and third conductive layers and the channel layer are formed of a polysilicon material.
4. The method of claim 1 , wherein forming the slit trench is performed by an anisotropic etching process such that the portion of the stack structure is vertically etched.
5. The method of claim 4 , wherein the anisotropic etching process includes an anisotropic dry etching process.
6. The method of claim 1 , wherein an isotropic etching process is performed such that at least the portion of the sacrificial layer and the portion of the memory layer are removed.
7. The method of claim 6 , wherein the isotropic etching process is performed by a wet etching process or dry etching process.
8. The method of claim 6 , wherein the isotropic etching process is performed using a material having a high etch rate with respect to the sacrificial layer.
9. The method of claim 1 , wherein the third conductive layer is selectively grown along surfaces of the channel layer and the second conductive layer.
10. The method of claim 1 , further comprising, before the portions of the sacrificial layer and the memory layer are removed, forming a spacer pattern on a partial side surface of the slit trench.
11. The method of claim 10 , wherein the spacer pattern is formed on side surfaces of fourth conductive layers, which are included in the stack structure, exposed through the side surface of slit trench among insulating layers and the fourth conductive layers.
12. The method of claim 10 , wherein the spacer pattern is formed of a material having an etch rate different from the sacrificial layer.
13. The method of claim 12 , wherein the spacer pattern is formed of a nitride layer, an Al203 layer, or a stacked layer of the nitride layer and the Al203 layer.
14. The method of claim 1 , wherein an upper surface of the first conductive layer is flat.
15. The method of claim 1 , wherein an upper surface of the second conductive layer is uneven by exposing the portion of the channel layer and the second conductive layer.