Power supply management device and memory system

1. A power supply management device comprising:

an input circuit configured to receive a first voltage and to output a voltage corresponding to the first voltage;

a first input terminal configured to receive a signal different from the first voltage; and

a first power supply circuit configured to receive the voltage corresponding to the first voltage from the input circuit, and to output a voltage obtained by converting the voltage corresponding to the first voltage,

wherein the first power supply circuit is further configured to output a second voltage responsive to a first signal being received by the first input terminal, and to output a third voltage different from the second voltage responsive to a second signal different from the first signal being received by the first input terminal.

2. The power supply management device according to claim 1 , further comprising:

a register circuit configured to store first setting information and second setting information,

wherein the first power supply circuit is configured to operate based on the first setting information responsive to the first signal being received by the first input terminal, and is configured to operate based on the second setting information responsive to the second signal being received by the first input terminal.

3. The power supply management device according to claim 2 ,

wherein the first signal is a signal of a first logic level and the second signal is a signal of a second logic level different from the first logic level.

4. The power supply management device according to claim 2 ,

wherein the register circuit is further configured to store third setting information, and

the first power supply circuit is configured to operate based on the third setting information responsive to a third signal different from the first signal and the second signal being received by the first input terminal.

5. The power supply management device according to claim 1 , further comprising:

a second input terminal configured to receive a signal different from the first voltage; and

a second power supply circuit configured to receive the voltage corresponding to the first voltage from the input circuit, and to output a voltage obtained by converting the voltage corresponding to the first voltage,

wherein the second power supply circuit is further configured to:

output a fourth voltage responsive to the first signal being received by the first input terminal and a third signal different from the first signal and the second signal being received by the second input terminal,

output a fifth voltage different from the fourth voltage responsive to the second signal being received by the first input terminal and the third signal being received by the second input terminal,

output a sixth voltage different from the fourth voltage and the fifth voltage responsive to the first signal being received by the first input terminal and a fourth signal different from the first signal, the second signal, and the third signal being received by the second input terminal, and

output a seventh voltage different from the fourth voltage, the fifth voltage, and the sixth voltage responsive to the second signal being received by the first input terminal and the fourth signal being received by the second input terminal.

6. The power supply management device according to claim 5 , further comprising:

a register circuit configured to store first setting information, second setting information, third setting information, and fourth setting information,

wherein the first power supply circuit and the second power supply circuit are configured to operate based on the first setting information responsive to the first signal being received by the first input terminal and the third signal being received by the second input terminal,

the first power supply circuit and the second power supply circuit are configured to operate based on the second setting information responsive to the second signal being received by the first input terminal and the third signal being received by the second input terminal,

the first power supply circuit and the second power supply circuit are configured to operate based on the third setting information responsive to the first signal being received by the first input terminal and the fourth signal being received by the second input terminal, and

the first power supply circuit and the second power supply circuit are configured to operate based on the fourth setting information responsive to the second signal being received by the first input terminal and the fourth signal being received by the second input terminal.

7. The power supply management device according to claim 6 ,

wherein the first signal is a signal of a first logic level and the second signal is a signal of a second logic level different from the first logic level, and

the third signal is a signal of a third logic level and the fourth signal is a signal of a fourth logic level different from the third logic level.

8. The power supply management device according to claim 6 ,

wherein the register circuit is further configured to store fifth setting information, sixth setting information, seventh setting information, eighth setting information, and ninth setting information, and

the first power supply circuit and the second power supply circuit are configured to operate based on the fifth setting information responsive to a fifth signal different from the first signal, the second signal, the third signal, and the fourth signal being received by the first input terminal and a sixth signal different from the first signal, the second signal, the third signal, the fourth signal, and the fifth signal being received by the second input terminal,

the first power supply circuit and the second power supply circuit are configured to operate based on the sixth setting information responsive to the fifth signal being received by the first input terminal and the third signal being received by the second input terminal,

the first power supply circuit and the second power supply circuit are configured to operate based on the seventh setting information responsive to the fifth signal being received by the first input terminal and the fourth signal being received by the second input terminal,

the first power supply circuit and the second power supply circuit are configured to operate based on the eighth setting information responsive to the first signal being received by the first input terminal and the sixth signal being received by the second input terminal, and

the first power supply circuit and the second power supply circuit are configured to operate based on the ninth setting information responsive to the second signal being received by the first input terminal and the sixth signal being received by the second input terminal.

9. The power supply management device according to claim 1 ,

wherein the power supply management device is a single integrated circuit, and the first input terminal is further configured to connect to a general purpose input/output (GPIO) circuit or an analog to digital (A/D) converter circuit.

10. A memory system comprising:

a storage unit which comprises a first memory;

a controller circuit configured to control the storage unit;

a power supply management device which comprises an input circuit configured to receive a first voltage and to output a voltage corresponding to the first voltage, a first input terminal configured to receive a signal different from the first voltage, and a first power supply circuit configured to receive the voltage corresponding to the first voltage from the input circuit, and to convert the voltage corresponding to the first voltage to output the converted voltage to the first memory or the controller circuit; and

a setting circuit configured to provide a setting signal to the first input terminal,

wherein the first power supply circuit is configured to output a second voltage responsive to the setting signal being a first signal and to output a third voltage responsive to the setting signal being a second signal.

11. The memory system according to claim 10 ,

wherein the power supply management device further comprises a register circuit configured to store first setting information and second setting information, and

the first power supply circuit is configured to operate based on the first setting information responsive to the first signal being received by the first input terminal, and is configured to operate based on the second setting information responsive to the second signal being received by the first input terminal.

12. The memory system according to claim 11 ,

wherein the first signal is a signal of a first logic level and the second signal is a signal of a second logic level different from the first logic level.

13. The memory system according to claim 11 ,

wherein the register circuit is further configured to store third setting information, and

the first power supply circuit is configured to operate based on the third setting information responsive to the setting signal being a third signal.

14. The memory system according to claim 10 ,

wherein the storage unit further comprises a second memory,

the power supply management device further comprises a second input terminal configured to receive a signal different from the first voltage and a second power supply circuit configured to convert a voltage corresponding to the first voltage to output the converted voltage to the second memory, and the second power supply circuit is further configured to:

output a fourth voltage responsive to the first signal being received by the first input terminal and a third signal different from the first signal and the second signal being received by the second input terminal,

output a fifth voltage different from the fourth voltage responsive to the second signal being received by the first input terminal and the third signal being received by the second input terminal,

output a sixth voltage different from the fourth voltage and the fifth voltage responsive to the first signal being received by the first input terminal and a fourth signal different from the first signal, the second signal, and the third signal being received by the second input terminal, and

output a seventh voltage different from the fourth voltage, the fifth voltage, and the sixth voltage responsive to the second signal being received by the first input terminal and the fourth signal being received by the second input terminal.

15. The memory system according to claim 14 ,

wherein the power supply management device further comprises a register circuit configured to store first setting information, second setting information, third setting information, and fourth setting information,

the first power supply circuit and the second power supply circuit are configured to operate based on the first setting information responsive to the first signal being received by the first input terminal and the third signal being received by the second input terminal,

the first power supply circuit and the second power supply circuit are configured to operate based on the second setting information responsive to the second signal being received by the first input terminal and the third signal being received by the second input terminal,

the first power supply circuit and the second power supply circuit are configured to operate based on the third setting information responsive to the first signal being received by the first input terminal and the fourth signal being received by the second input terminal, and

the first power supply circuit and the second power supply circuit are configured to operate based on the fourth setting information responsive to the second signal being received by the first input terminal and the fourth signal being received by the second input terminal.

16. The memory system according to claim 15 ,

wherein the first signal is a signal of a first logic level and the second signal is a signal of a second logic level different from the first logic level, and

the third signal is a signal of a third logic level and the fourth signal is a signal of a fourth logic level different from the third logic level.

17. The memory system according to claim 15 ,

wherein the register circuit is further configured to store fifth setting information, sixth setting information, seventh setting information, eighth setting information, and ninth setting information, and

the first power supply circuit and the second power supply circuit are configured to operate based on the fifth setting information responsive to a fifth signal different from the first signal, the second signal, the third signal, and the fourth signal being received by the first input terminal and a sixth signal different from the first signal, the second signal, the third signal, the fourth signal, and the fifth signal being received by the second input terminal,

the first power supply circuit and the second power supply circuit are configured to operate based on the sixth setting information responsive to the fifth signal being received by the first input terminal and the third signal being received by the second input terminal,

the first power supply circuit and the second power supply circuit are configured to operate based on the seventh setting information responsive to the fifth signal being received by the first input terminal and the fourth signal being received by the second input terminal,

the first power supply circuit and the second power supply circuit are configured to operate based on the eighth setting information responsive to the first signal being received by the first input terminal and the sixth signal being received by the second input terminal, and

the first power supply circuit and the second power supply circuit are configured to operate based on the ninth setting information responsive to the second signal being received by the first input terminal and the sixth signal being received by the second input terminal.

18. The memory system according to claim 10 ,

wherein the power supply management device is a single integrated circuit, and the first input terminal is further configured to connect to a general purpose input/output (GPIO) circuit or an analog to digital (A/D) converter circuit.

19. The memory system according to claim 10 ,

wherein the setting circuit comprises a first circuit and a second circuit,

a node of the setting circuit connected to the first input terminal is connected to a power supply via the first circuit and is connected to a ground via the second circuit, and

the setting signal is the first signal and a resistance value of the first circuit is smaller than a resistance value of the second circuit, or the setting signal is the second signal and a resistance value of the first circuit is larger than a resistance value of the second circuit.

20. The memory system according to claim 10 ,

wherein the controller circuit comprises an interface circuit connectable to external host equipment, and

the interface circuit is a circuit based on one of Serial Attached SCSI (SAS), PCI EXPRESS (PCIe), Serial Advanced Technology Attachment (SATA), or Universal Serial Bus (USB).