IP Library › Granted Patent US 12,321,618
Granted Patent B2
US 12,321,618 · App. 17/948,858 · Granted Jun 3, 2025

Operating method of storage device, operating method of host, and storage system including the storage device and the host

Inventors: Joonmin Park (Seoul, KR); Byoungsul Kim (Suwon-si, KR); Hyunsoo Shim (Uijeongbu-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F3/0625G06F3/0659G06F3/0679G11C16/30
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Quick Facts
Patent No.
US 12,321,618
App. No.
17/948,858
Granted
Jun 3, 2025
Kind
B2
Abstract

An operating method of a storage device including a non-volatile memory is provided. The operating method includes: receiving a first source voltage through a first voltage signal pin; based on the first source voltage different from a target voltage of the storage device, controlling the first source voltage to the target voltage; receiving a command, which indicates an information request associated with an operation voltage of the storage device, from a host; transmitting a response, which corresponds to the information request, to the host by using the storage device; receiving a second source voltage which has a voltage level different from the first source voltage, through the first voltage signal pin; and providing the second source voltage to the non-volatile memory.

Claims (28)

1. An operating method of a storage device including a non-volatile memory, the operating method comprising:

receiving a first source voltage generated by a power management integrated circuit through a first voltage signal pin;

based on the first source voltage being different from a target voltage of the storage device, controlling the first source voltage to the target voltage while receiving the first source voltage generated by the power management integrated circuit;

receiving a command, which indicates an information request associated with an operation voltage of the storage device, from a host;

transmitting a response, which corresponds to the information request, to the host by using the storage device;

receiving a second source voltage which is generated by the power management integrated circuit and has a voltage level different from the first source voltage, through the first voltage signal pin; and

providing the second source voltage to the non-volatile memory,

wherein the receiving the second source voltage comprises:

generating an internal voltage control signal indicating whether to convert the second source voltage, based on the second source voltage; and

controlling the second source voltage to the target voltage based on the internal voltage control signal.

2. The operating method of claim 1 , wherein the controlling the first source voltage to the target voltage comprises, based on the first source voltage being higher than the target voltage, controlling the first source voltage to the target voltage.

3. The operating method of claim 1 , wherein the first source voltage is higher than the operation voltage.

4. The operating method of claim 1 , wherein the generating the internal voltage control signal comprises generating the internal voltage control signal based on a comparison of the second source voltage and the target voltage.

5. The operating method of claim 4 , wherein the generating the internal voltage control signal comprises:

based on the second source voltage being lower than or equal to the target voltage, generating a first internal voltage control signal for maintaining the second source voltage; and

based on the second source voltage being higher than the target voltage, generating a second internal voltage control signal for converting the second source voltage.

6. The operating method of claim 5 , wherein the controlling the second source voltage comprises controlling the second source voltage to the target voltage based on the second internal voltage control signal.

7. The operating method of claim 5 , wherein the first internal voltage control signal and the second internal voltage control signal have different logic levels.

8. The operating method of claim 1 , further comprising receiving a third source voltage through a second voltage signal pin,

wherein the receiving the second source voltage comprises:

generating the internal voltage control signal indicating whether to convert the second source voltage based on the second source voltage and the third source voltage; and

controlling the second source voltage to the target voltage based on the internal voltage control signal.

9. The operating method of claim 1 , wherein the second source voltage and the operation voltage have a same voltage level.

10. A storage system comprising:

a power management integrated circuit configured to generate a source voltage;

a storage device configured to control a first source voltage to a target voltage of the storage device while the first source voltage is received from the power management integrated circuit; and

a host configured to receive data associated with an operation voltage of the storage device from the storage device and control the power management integrated circuit to provide the storage device with a second source voltage having a voltage level different from the first source voltage, based on the data,

wherein the storage device is further configured to generate an internal voltage control signal indicating whether to convert the second source voltage, based on the second source voltage, and convert the second source voltage to the target voltage based on the internal voltage control signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2022
From: PARK, JOONMIN; KIM, BYOUNGSUL; SHIM, HYUNSOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 061156/0476 →
Priority Claims (1)
KR 10-2021-0127539 · Sep 27, 2021 · national
Continuity (1)
Related Publication 20230100119A1 · Mar 30, 2023
References Cited (17)
US 7535307B2 · Lee · 2009 [cited by applicant]
US 7617335B2 · Choi et al. · 2009 [cited by applicant]
US 7639540B2 · Kim et al. · 2009 [cited by applicant]
US 7715268B2 · Hsieh et al. · 2010 [cited by applicant]
US 7760574B2 · Chen et al. · 2010 [cited by applicant]
US 10387690B2 · Kothamasu et al. · 2019 [cited by applicant]
US 10395721B1 · Prather et al. · 2019 [cited by applicant]
US 10438668B2 · Okamoto · 2019 [cited by applicant]
US 10453541B1 · Rowley et al. · 2019 [cited by applicant]
US 20180101492A1 · Cho · 2018 [cited by examiner]
US 20200333818A1 · Yun · 2020 [cited by examiner]
US 20210065772A1 · Suh et al. · 2021 [cited by applicant]
KR 100799038B1 · 2008 [cited by applicant]
KR 1020180038939A · 2018 [cited by applicant]
KR 1020210040173A · 2021 [cited by applicant]
Communication dated Feb. 14, 2023 by the European Property Office in counterpart EP Patent Application No. 22195150.2. [cited by applicant]
Office Action dated Apr. 2, 2025, issued by Korean Intellectual Property Office in Korean Patent Application No. 10-2021-0127539. [cited by applicant]