IP Library › Granted Patent US 10,438,852
Granted Patent B2
US 10,438,852 · App. 15/770,258 · Granted Oct 8, 2019

Semiconductor device

Inventor: Noriyuki Kakimoto (Kariya, JP)
Assignee: DENSO CORPORATION
H01L21/823418H01L27/06H01L27/0727H01L27/088H01L29/739H01L29/78H01L29/861H01L29/868H01L29/87H02M1/08H02M7/003H01L29/407H02M7/538
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Quick Facts
Patent No.
US 10,438,852
App. No.
15/770,258
Granted
Oct 8, 2019
Kind
B2
Abstract

A semiconductor device includes: reverse conducting switching elements-in each of which a diode element and a switching element are arranged in parallel on a single semiconductor substrate; a driver applying a gate voltage to a plurality of gate electrodes in the reverse conducting switching elements; and a mode determination unit determining whether a forward conduction mode in which a current mainly flows through the switching element or a reverse conduction mode in which the current flows through the diode element is being operated.

Claims (47)

1. A semiconductor device comprising:

a reverse conducting switching device including a diode device and a switching device, which are arranged in parallel at a single semiconductor substrate;

a driver configured to apply a gate voltage to a plurality of gate electrodes included in the reverse conducting switching device; and

a mode determination unit configured to determine whether

a forward conduction mode in which a current flows mainly in the switching device, or

a reverse conduction mode in which the current flows mainly in the diode device is operated in the reverse conducting switching device,

wherein the diode device includes

a first impurity region having a first conduction type,

a second impurity region having a second conduction type which is coupled to the first impurity region,

a first electrode configured to electrically connected to the first impurity region, and

a second electrode configured to electrically connected to the second impurity region,

wherein an inverted layer is generated in the first impurity region in response to applying a predetermined gate voltage to the plurality of gate electrodes, and

wherein the switching device and the diode device commonly share the first electrode and the second electrode, respectively,

wherein the switching device is turned on to control a current flow between the first electrode and the second electrode in response to applying the predetermined gate voltage to the plurality of gate electrodes,

wherein the plurality of gate electrodes includes

a first gate electrode to which a first gate voltage for turning on the switching device is input, and

a second gate electrode to which a second gate voltage is input, the second gate voltage being controlled independently of the first gate voltage, the second gate voltage having a potential level same as a potential level at the second electrode or the second gate voltage having a polarity opposite from a polarity of the first gate voltage with reference to the potential level at the second electrode,

wherein one part of the plurality of gate electrodes in the diode device includes at least the second gate electrode, and another part of the plurality of gate electrodes in the switching device includes at least the first gate electrode, and

wherein the second gate voltage is applied to the second gate electrode

in response to determining the reverse conducting switching device being operated in the reverse conduction mode based on the current flowing between the first electrode and the second electrode, or

in response to the mode determination unit being unable to determine whether the reverse conduction mode or the forward conduction mode is operated in the reverse conducting switching device.

2. The semiconductor device according to claim 1 ,

wherein the driver is configured to apply a PWM-controlled gate voltage including at least two respective values of a high voltage level and a low voltage level to the second gate electrode

in response to determining the reverse conducting switching device being operated in the reverse conduction mode, or

in response to the mode determination unit being unable to determine whether the reverse conduction mode or the forward conduction mode is operated in the reverse conducting switching device,

wherein the low voltage level has a polarity opposite from the polarity of the first gate voltage with reference to the potential level at the second electrode.

3. The semiconductor device according to claim 1 ,

wherein the driver is configured to apply, to the second gate electrode, a gate voltage having a polarity opposite from the polarity of the first gate voltage with reference to the potential level at the second electrode

in response to determining the reverse conducting switching device being operated in the reverse conduction mode, or

in response to the mode determination unit being unable to determine whether the reverse conduction mode or the forward conduction mode is operated in the reverse conducting switching device.

4. The semiconductor device according to claim 1 ,

wherein, in response to determining the reverse conducting switching device being operated in the reverse conduction mode, the driver is configured to

apply a gate voltage, which is equal to the potential level at the second electrode, to the second gate electrode when a diode current flowing between the first electrode and the second electrode is equal to or larger than a predetermined threshold, and

apply a gate voltage having a polarity opposite from the polarity of the first gate voltage with reference to the potential level at the second electrode to the second gate electrode when the diode current is smaller than the predetermined threshold.

5. The semiconductor device according to claim 1 ,

wherein a gate voltage having a polarity, which is opposite from the polarity of the first gate voltage with reference to the potential level at the second electrode, is applied to the plurality of gate electrodes in a combined region, which is a boundary region between a region where the diode device is arranged and a region where the switching device is arranged.

6. The semiconductor device according to claim 1 ,

wherein the first gate voltage is applied to the plurality of gate electrodes in a combined region, which is a boundary region between a region where the diode device is arranged and a region where the switching device is arranged.

7. The semiconductor device according to claim 1 ,

wherein the one part of the plurality of gate electrodes in the switching device includes the second gate electrode.

8. The semiconductor device according to claim 1 ,

wherein a gate voltage applied to the first gate electrode by the driver is equal to the potential level at the second electrode in response to determining the reverse conducting switching device being operated in the reverse conduction mode.

9. The semiconductor device according to claim 1 ,

wherein the first impurity region at the diode device includes a barrier region having the first conduction type, which is adjacent to the second impurity region, and

wherein the inverted layer is generated at the barrier region in response to applying the predetermined gate voltage to the plurality of gate electrodes.

10. The semiconductor device according to claim 1 ,

wherein the diode device further includes a third impurity region having the second conduction type in a current path between the first electrode and the second electrode, the third impurity region arranged to be at the first impurity region and arranged to be isolated from the second impurity region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2018
From: KAKIMOTO, NORIYUKI
To: DENSO CORPORATION
Reel/Frame 045608/0201 →
Priority Claims (1)
JP 2016-013713 · Jan 27, 2016 · national
Continuity (1)
Related Publication 20180308757A1 · Oct 25, 2018
Cited By (2)
US 12,342,556 US 12,507,428