Semiconductor device including transistor portion and diode portion
Provided is a semiconductor device in which a lifetime control region including a lifetime killer is provided, below a base region, from at least a part of a transistor portion to a diode portion, the transistor portion includes: a main region spaced apart from the diode portion in a top view; a boundary region located between the main region and the diode portion and overlapping the lifetime control region in a top view; and a plurality of gate trench portions provided from an upper surface of the semiconductor substrate to a drift region through the base region, the plurality of gate trench portions include: a first gate trench portion provided in the main region; and a second gate trench portion provided in the boundary region, and a signal transmission timing of the first gate trench portion is different from a signal transmission timing of the second gate trench portion.
1 . A semiconductor device, comprising:
a semiconductor substrate having a transistor portion and a diode portion, wherein
both the transistor portion and the diode portion include:
a drift region of a first conductivity type provided in the semiconductor substrate; and
a base region of a second conductivity type provided above the drift region in the semiconductor substrate,
a lifetime control region that includes a lifetime killer is provided from at least a part of the transistor portion to the diode portion below the base region,
the transistor portion includes:
a main region spaced apart from the diode portion in a top view of the semiconductor substrate;
a boundary region located between the main region and the diode portion and overlapping the lifetime control region in a top view of the semiconductor substrate; and
a plurality of gate trench portions provided from an upper surface of the semiconductor substrate to the drift region through the base region,
the plurality of gate trench portions includes:
a first gate trench portion provided in the main region; and
a second gate trench portion provided in the boundary region,
a signal transmission timing of the first gate trench portion is different from a signal transmission timing of the second gate trench portion, and
a uniform thickness of a gate dielectric film of the first gate trench portion is different from a uniform thickness of a gate dielectric film of the second gate trench portion,
wherein the first gate trench portion and the second gate trench portion are provided to a same depth from the upper surface of the semiconductor substrate.
2 . The semiconductor device according to claim 1 , comprising:
a first gate pad configured to be electrically connected to the first gate trench portion; and
a second gate pad configured to be electrically connected to the second gate trench portion.
3 . The semiconductor device according to claim 2 , wherein
a gate capacitance component of the first gate trench portion is different from a gate capacitance component of the second gate trench portion.
4 . The semiconductor device according to claim 3 , wherein
a gate dielectric film of the first gate trench portion is formed of a material different from a material of a gate dielectric film of the second gate trench portion.
5 . The semiconductor device according to claim 2 , wherein
a gate dielectric film of the first gate trench portion is formed of a material different from a material of a gate dielectric film of the second gate trench portion.
6 . The semiconductor device according to claim 1 , wherein
a gate capacitance component of the first gate trench portion is different from a gate capacitance component of the second gate trench portion.
7 . The semiconductor device according to claim 6 , wherein
the gate dielectric film of the second gate trench portion is uniformly thicker than the gate dielectric film of the first gate trench portion.
8 . The semiconductor device according to claim 7 , wherein
a gate dielectric film of the first gate trench portion is formed of a material different from a material of a gate dielectric film of the second gate trench portion.
9 . The semiconductor device according to claim 6 , wherein
the gate dielectric film of the first gate trench portion is uniformly thicker than the gate dielectric film of the second gate trench portion.
10 . The semiconductor device according to claim 6 , wherein
a gate dielectric film of the first gate trench portion is formed of a material different from a material of a gate dielectric film of the second gate trench portion.
11 . The semiconductor device according to claim 6 , wherein
a gate dielectric film of the first gate trench portion is formed of a material different from a material of a gate dielectric film of the second gate trench portion.
12 . The semiconductor device according to claim 1 , wherein
a gate dielectric film of the first gate trench portion is formed of a material different from a material of a gate dielectric film of the second gate trench portion.
13 . The semiconductor device according to claim 12 , wherein
the gate dielectric film of the second gate trench portion is formed of a material having a relative dielectric constant lower than a relative dielectric constant of the material of the gate dielectric film of the first gate trench portion.
14 . The semiconductor device according to claim 12 , wherein
the gate dielectric film of the first gate trench portion is formed of a material having a relative dielectric constant lower than a relative dielectric constant of the gate dielectric film of the second gate trench portion.