Cascode heterojunction bipolar transistor

1. A method of fabricating a structure using a device layer of a silicon-on-insulator substrate, the method comprising:

forming a first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor in the device layer;

epitaxially growing a first base layer of the first heterojunction bipolar transistor on the device layer with an intrinsic base portion arranged on the first emitter;

epitaxially growing a first collector of the first heterojunction bipolar transistor on the intrinsic base portion of the first base layer;

epitaxially growing a second base layer of the second heterojunction bipolar transistor on the device layer with an intrinsic base portion arranged on the second collector;

epitaxially growing a second emitter of the second heterojunction bipolar transistor on the intrinsic base portion of the second base layer; and

forming a connection between the first emitter and the second collector.

2. The method of claim 1 wherein the first base layer is composed of silicon-germanium epitaxially grown with a first profile of germanium content, and the second base layer is composed of silicon-germanium epitaxially grown with a second profile of germanium content that is equal to the first profile of germanium content.

3. The method of claim 1 wherein forming the connection between the second emitter and the first collector comprises:

forming a doped region in the device layer,

wherein the doped region is arranged in the device layer to couple the first emitter with the second collector.

4. The method of claim 3 wherein forming the connection between the first emitter and the second collector further comprises:

siliciding at least a section of the doped region between the first emitter and the second collector.

5. The method of claim 1 further comprising:

forming a dielectric isolation region that penetrates through the device layer and that is arranged between the first emitter and the second collector.

6. The method of claim 5 wherein forming the connection between the first emitter and the second collector further comprises:

forming an interconnect structure that includes one or more conductive features connecting the first emitter with the second collector.

7. The method of claim 1 further comprising:

implanting the device layer to form a first doped region and a second doped region separated by a spacing equal to a dimension of the first emitter or to a dimension of the second collector.

8. The method of claim 7 wherein the second doped region is arranged in the device layer to couple the first emitter with the second collector.

9. The method of claim 1 further comprising:

depositing a plurality of non-conductor layers on the device layer; and

forming a first opening in the non-conductor layers that is aligned with the first emitter,

wherein the first base layer and the first collector are epitaxially grown inside the first opening.

10. The method of claim 9 further comprising:

forming a second opening in the non-conductor layers that is aligned with the second collector,

wherein the second base layer and the second emitter are epitaxially grown inside the second opening.