Memory cell structure
A memory cell structure includes a plurality of write lines arranged for writing a synapse state to a synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write lines being used for writing the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing one of a second set of states to each unit cell included in the corresponding cell component, and the first set depending on the second set.
1. A memory cell structure comprising:
a plurality of write lines configured to write a synapse state to a synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write lines being configured to write the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing a second set of states to each unit cell included in the corresponding cell component, the first set being dependent on the second set.
2. The memory cell structure of claim 1 , wherein each unit cell is a resistance and the first and second sets of states include states regarding conductance of the resistance.
3. The memory cell structure of claim 1 , wherein each unit cell is a capacitor and the first and second sets of states include states regarding capacitance of the capacitor.
4. The memory cell structure of claim 1 , wherein the first and second sets each have a predetermined number of states equal to two.
5. The memory cell structure of claim 4 , wherein:
an i-th cell component of the plurality of cell components includes 2 i−1 unit cells, where i is a natural number; and
each of the states in the first set is 2 i−1 times of a corresponding one of the states in the second set.
6. The memory cell structure of claim 1 , wherein the first and second sets each have a predetermined number of states equal to three.
7. The memory cell structure of claim 6 , wherein:
an i-th cell component of the plurality of cell components includes 3 i−1 unit cells, where i is a natural number; and
each of the states in the first set is 3 i−1 times of a corresponding one of the states in the second set.
8. The memory cell structure of claim 1 , further comprising a read line configured to read the synapse state from the synapse memory cell by reading the first set of states from the plurality of cell components simultaneously.
9. A memory cell system comprising:
a plurality of write drivers configured to write a synapse state to the synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write drivers being configured to write the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing a second set of states to each unit cell included in the corresponding cell component, the first set being dependent on the second set.
10. The memory cell system of claim 9 , wherein each unit cell is a resistance and the first and second sets of states include states regarding conductance of the resistance.
11. The memory cell system of claim 9 , wherein each unit cell is a capacitor and the first and second sets of states include states regarding capacitance of the capacitor.
12. The memory cell system of claim 9 , wherein:
the first and second sets each have a predetermined number of states equal to two;
i-th cell component of the plurality of cell components includes 2 i−1 unit cells, where i is a natural number; and
each of the predetermined number of states in the first set is 2 i−1 times of a corresponding one of the predetermined number of states in the second set.
13. The memory cell system of claim 9 , wherein:
the first and second sets each have a predetermined number of states equal to three;
i-th cell component of the plurality of cell components includes 3 i−1 unit cells, where i is a natural number; and
each of the predetermined number of states in the first set is 3 i−1 times of a corresponding one of the predetermined number of states in the second set.
14. The memory cell system of claim 9 , further comprising a read driver configured to read the synapse state from the synapse memory cell by reading the first set of states from the plurality of cell components simultaneously.
15. A method for fabricating a memory cell structure, the method comprising:
arranging a plurality of write lines configured to write a synapse state to a synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write lines being configured to write the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing a second set of states to each unit cell included in the corresponding cell component, the first set being dependent on the second set.
16. The method of claim 15 , wherein each unit cell is a resistance and the first and second sets of states include states regarding conductance of the resistance.
17. The method of claim 15 , wherein each unit cell is a capacitor and the first and second sets of states include states regarding capacitance of the capacitor.
18. The method of claim 15 , wherein:
the first and second sets each have a predetermined number of states equal to two,
an i-th cell component of the plurality of cell components includes 2 i−1 unit cells, where i is a natural number; and
each of the states in the first set is 2 i−1 times of a corresponding one of the states in the second set.
19. The method of claim 15 , wherein:
the first and second sets each have a predetermined number of states equal to three;
an i-th cell component of the plurality of cell components includes 3 i−1 unit cells, where i is a natural number; and
each of the states in the first set is 3 i−1 times of a corresponding one of the states in the second set.
20. The method of claim 15 , further comprising a read line configured to read the synapse state from the synapse memory cell by reading the first set of states from the plurality of cell components simultaneously.