IP Library › Granted Patent US 10,446,547
Granted Patent B2
US 10,446,547 · App. 16/394,578 · Granted Oct 15, 2019

Super-saturation current field effect transistor and trans-impedance MOS device

Inventors: Susan Marya Schober (Newport Beach, CA); Robert C. Schober (Huntington Beach, CA)
Assignee: Circuit Seed, LLC
H01L27/092H01L21/823814H01L27/0207H03F1/086H03F3/04H03F3/165H03F3/45179H03F2203/45246
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Quick Facts
Patent No.
US 10,446,547
App. No.
16/394,578
Granted
Oct 15, 2019
Kind
B2
Abstract

The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuites.

Claims (22)

1. A field effect transistor comprising:

a. a source diffusion connected to a source terminal;

b. a drain diffusion connected to a drain terminal;

c. a third diffusion connected to a bidirectional current terminal (iPort), interposed between the source and drain diffusions, defining a source channel segment between the source diffusion and the third diffusion, and a drain channel segment between the drain diffusion and the third diffusion;

d. a gate capacitively coupled with the source channel segment and the drain channel segment,

wherein

a ratio of a width to a length of the source channel segment and a ratio of a width to a length of the drain channel segment are different.

2. The field effect transistor of claim 1 , wherein a trans-resistance of the field effect transistor is established by a ratio of:

a. the ratio of the width and the length of the drain channel segment; and

b. the ratio of the width and the length of the source channel segment.

3. The field effect transistor of claim 2 , wherein a current applied at the bidirectional current terminal is converted to a voltage by the trans-resistance.

4. A field effect transistor comprising:

a. a source diffusion connected to a source terminal;

b. a drain diffusion connected to a drain terminal;

c. an intermediate diffusion connected to an intermediate bidirectional current terminal (iPort), the intermediate diffusion interposed between the source and drain diffusions, and defining a source channel segment between the source diffusion and the intermediate diffusion, and a drain channel segment between the drain diffusion and the intermediate diffusion;

d. a first gate terminal capacitively coupled with the source channel segment; and

e. a second gate terminal capacitively coupled with the drain channel segment,

a ratio of a width to a length of the source channel segment and a ratio of a width to a length of the drain channel segment are different.

5. The field effect transistor of claim 4 , wherein a trans-resistance of the field effect transistor is established by a ratio of:

a. the ratio of the width and the length of the drain channel segment; and

b. the ratio of the width and the length of the source channel segment.

6. The field effect transistor of claim 5 , wherein a current applied at the bidirectional current terminal is converted to a voltage by the trans-resistance.

Continuity (3)
Continuation 15748908
Provisional Application 62267174 · Dec 14, 2015
Related Publication 20190252382A1 · Aug 15, 2019
Cited By (1)
US 12,191,812