Low off-leakage current switch
Low-leakage switch circuit techniques to reduce leakage current of an off-state switch, while maintaining a low on-resistance. The low-leakage switch circuit may allow measurement of low current signals in a transimpedance amplifier with improved accuracy without, the need for calibration. The low-leakage switch circuit may include a bootstrapping path connecting two or more terminals or voltage nodes of an off-state switch in the switch circuit. The bootstrapping path is configured to bootstrap major leakage current contributors in the switch circuit, such as the substrate diode leakage, the subthreshold leakage, or combinations thereof.
1. A low off-leakage switched gain trans-impedance amplifier (TIA) circuit having an input terminal to receive an input current, the switched gain TIA circuit comprising:
a first switch including a first transistor circuit coupled in series with a second transistor circuit via a first midpoint node, wherein a back-gate node of the second transistor circuit is coupled to the first midpoint node, and wherein the first switch has an ON state and an OFF state;
an amplifier circuit including an output node coupled to an input node of the first switch and an input node of a second switch; and
a bootstrapping circuit configured to receive a voltage and generate an output signal selectively coupleable to the first midpoint node to bias the first midpoint node to a representation of the voltage based on whether the first switch is in the OFF state,
wherein an output of the first switch is coupled to a first resistor in a first feedback path of the TIA circuit.
2. The switched gain amplifier TIA circuit of claim 1 , wherein the bootstrapping circuit includes:
a bootstrapping amplifier circuit including a first bootstrapping input terminal coupled to the input terminal and configured to receive the voltage; and
a multiplexer circuit coupled to an output of the bootstrapping amplifier circuit, wherein the multiplexer circuit includes a selectable output node to provide the output signal of the bootstrapping circuit.
3. The switched gain amplifier TIA circuit of claim 2 , wherein the bootstrapping amplifier circuit is arranged in a unity gain configuration.
4. The switched gain amplifier TIA circuit of claim 1 , wherein the first midpoint node is coupled to a first terminal of the second transistor circuit, and wherein the back-gate node of the second transistor circuit is coupled to the first terminal of the second transistor circuit.
5. The switched gain amplifier TIA circuit of claim 1 , wherein the first transistor circuit and the second transistor circuit include field-effect transistors.
6. The switched gain amplifier TIA circuit of claim 1 , wherein the first transistor circuit and the second transistor circuit include transmission gate circuits, and wherein the transmission gate circuits include a p-type field-effect transistor and an n-type field-effect transistor.
7. The switched gain amplifier TIA circuit of claim 1 , comprising:
the second switch including a third transistor circuit coupled in series with a fourth transistor circuit via a second midpoint node, wherein a back-gate node of the fourth transistor circuit is coupled to the second midpoint node, wherein the second switch has an ON state and an OFF state, wherein the second switch is configured to be in the ON state when the first switch is in the OFF state.
8. A method of operating a low off-leakage switched gain amplifier circuit having an input terminal to receive an input current, the method comprising:
coupling a first switch including a first transistor circuit in series with a second transistor circuit via a first midpoint node, wherein a back-gate node of the second transistor circuit is coupled to the first midpoint node, and wherein the first switch has an ON state and an OFF state;
coupling a second switch including a third transistor circuit in series with a fourth transistor circuit via a second midpoint node, wherein a back-gate node of the fourth transistor circuit is coupled to the second midpoint node, wherein the second switch has an ON state and an OFF state, and wherein the second switch is configured to be in the ON state when the first switch is in the OFF state;
receiving, using a trans-impedance amplifier (TIA) circuit, the input current, wherein the TIA circuit has an output node coupled to an input node of the first switch and an input node of the second switch;
receiving, using a bootstrapping circuit, a voltage and generating an output signal selectively coupleable to the first midpoint node and the second midpoint node to bias the first midpoint node or the second midpoint node to a representation of the voltage based on whether the first switch is in the OFF state or the second switch is in the OFF state; and
coupling an output of the first switch to a first resistor in a first feedback path of the TIA circuit, and coupling an output of the second switch to a second resistor in a second feedback path of the TIA circuit.
9. The method of claim 8 , comprising:
coupling a bootstrapping amplifier circuit to a multiplexer circuit.
10. The method of claim 9 , comprising:
coupling the bootstrapping amplifier circuit in a unity gain configuration.
11. The method of claim 9 , comprising:
selecting an output node of the multiplexer circuit to provide the output signal of the bootstrapping circuit.
12. The method of claim 8 , comprising:
coupling the first midpoint node to a first terminal of the second transistor circuit, and coupling the back-gate node of the second transistor circuit to the first terminal of the second transistor circuit.
13. The method of claim 8 , wherein the first switch and the second switch form a first switch circuit, the method of claim 8 comprising:
coupling a second switch circuit to the first switch circuit to form a Kelvin switching configuration.
14. A low off-leakage switched gain trans-impedance amplifier (TIA) circuit having an input terminal to receive an input current, the switched gain TIA circuit comprising:
a first switch including a first transistor circuit coupled in series with a second transistor circuit via a first midpoint node, wherein a back-gate node of the second transistor circuit is coupled to the first midpoint node, and wherein the first switch has an ON state and an OFF state;
a second switch including a third transistor circuit coupled in series with a fourth transistor circuit via a second midpoint node, wherein a back-gate node of the fourth transistor circuit is coupled to the second midpoint node, wherein the second switch has an ON state and an OFF state, wherein the second switch is configured to be in the ON state when the first switch is in the OFF state;
an amplifier circuit including an output node coupled to an input node of the first switch and an input node of the second switch; and
a bootstrapping circuit configured to receive a voltage and generate an output signal selectively coupleable to the first midpoint node and the second midpoint node to bias the first midpoint node or the second midpoint node to a representation of the voltage based on whether the first switch is in the OFF state or the second switch is in the OFF state,
wherein an output of the first switch is coupled to a first resistor in a first feedback path of the TIA circuit, and wherein an output of the second switch is coupled to a second resistor in a second feedback path of the TIA circuit.
15. The switched gain amplifier TIA circuit of claim 14 , wherein the bootstrapping circuit includes:
a bootstrapping amplifier circuit including a first bootstrapping input terminal coupled to the input terminal and configured to receive the voltage; and
a multiplexer circuit coupled to an output of the bootstrapping amplifier circuit, wherein the multiplexer circuit includes a selectable output node to provide the output signal of the bootstrapping circuit.
16. The switched gain amplifier TIA circuit of claim 15 , wherein the bootstrapping amplifier circuit is arranged in a unity gain configuration.
17. The switched gain amplifier TIA circuit of claim 14 , wherein the first midpoint node is coupled to a first terminal of the second transistor circuit, and wherein the back-gate node of the second transistor circuit is coupled to the first terminal of the second transistor circuit.
18. The switched gain amplifier TIA circuit of claim 14 , wherein the first transistor circuit, the second transistor circuit, the third transistor circuit, and the fourth transistor circuit include field-effect transistors.
19. The switched gain amplifier TIA circuit of claim 14 , wherein the first transistor circuit, the second transistor circuit, the third transistor circuit, and the fourth transistor circuit include transmission gate circuits, and wherein the transmission gate circuits include a p-type field-effect transistor and an n-type field-effect transistor.
20. The switched gain amplifier TIA circuit of claim 14 , wherein the first switch and the second switch form a first switch circuit, wherein the switched gain amplifier circuit of claim 1 includes:
a second switch circuit including:
a first switch including a first transistor circuit coupled in series with a second transistor circuit via a first midpoint node, wherein a back-gate node of the second transistor circuit is coupled to the first midpoint node, and wherein the first switch has an ON state and an OFF state; and
a second switch including a third transistor circuit coupled in series with a fourth transistor circuit via a second midpoint node, wherein a back-gate node of the fourth transistor circuit is coupled to the second midpoint node, wherein the second switch has an ON state and an OFF state, and wherein the second switch is configured to be in the ON state when the first switch is in the ON state,
wherein the first switch circuit and the second switch circuit are coupled in series, and
wherein an output of the second switch circuit is configured to provide an output signal of the switched gain amplifier circuit.