Negative capacitance integration through a gate contact
A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.
1. A semiconductor device, comprising:
a gate disposed over an active area of a semiconductor substrate and extending laterally over the semiconductor substrate outside of the active area;
a gate contact disposed over the gate outside of the active area;
a ferroelectric layer disposed between the gate contact and the gate outside of the active area; and
a template layer disposed over the gate outside of the active area, wherein the ferroelectric layer is disposed directly over the template layer, wherein the template layer comprises a crystalline material having an average grain size of less than 10 nm.
2. The device of claim 1 , wherein the gate comprises a gate dielectric and a gate conductor disposed over the gate dielectric, and the ferroelectric layer is disposed directly over the gate conductor.
3. The device of claim 2 , wherein the gate conductor comprises tungsten.
4. The device of claim 1 , wherein the template layer comprises titanium nitride or tantalum nitride.
5. The device of claim 1 , wherein the template layer is adapted to promote crystallization and growth of grains within the ferroelectric layer.
6. The device of claim 1 , further comprising a dielectric layer disposed over the gate, wherein the gate contact is disposed within a trench that extends through the dielectric layer.
7. The device of claim 6 , further comprising a conformal first electrode disposed over sidewalls of the trench and directly over a gate at a bottom of the trench.
8. The device of claim 7 , wherein the ferroelectric layer is disposed directly over the conformal first electrode within the trench.
9. The device of claim 7 , wherein the gate contact is disposed within the trench over the ferroelectric layer and the first electrode, and further comprising an isolation dielectric disposed over sidewalls of a trench between the gate contact and the first electrode.
10. The device of claim 6 , further comprising a sidewall spacer disposed over sidewalls of the trench, wherein the ferroelectric layer is disposed over the sidewall spacer between opposing sidewalls.
11. The device of claim 10 , wherein the sidewall spacer comprises silicon dioxide, silicon nitride or a high-k dielectric.
12. A method of fabricating a semiconductor device, comprising:
forming a gate over an active area of a semiconductor substrate, wherein the gate extends laterally over the semiconductor substrate outside of the active area;
forming a template layer over the gate outside of the active area, wherein the template layer comprises a crystalline material having an average grain size of less than 10 nm;
forming a ferroelectric layer directly over the template layer; and
forming a gate contact over the ferroelectric layer.
13. The method of claim 12 , further comprising:
forming a dielectric layer over the gate;
forming a trench extending through the dielectric layer outside of the active area and exposing a top surface of the gate;
forming a first electrode over sidewalls of the trench and directly over the gate at a bottom of the trench; and
forming the ferroelectric layer over the first electrode.
14. The method of claim 12 , further comprising:
forming a sidewall spacer over sidewalls of a trench; and
forming the ferroelectric layer between opposing sidewalls of the sidewall spacer.
15. A semiconductor device, comprising:
a gate disposed over an active area of a semiconductor substrate;
a gate contact disposed over the gate;
a dielectric layer disposed over the gate, wherein the gate contact is disposed within a trench that extends through the dielectric layer;
a ferroelectric layer disposed between the gate contact and the gate; and
a sidewall spacer disposed over sidewalls of the trench, wherein the ferroelectric layer is disposed over the sidewall spacer between opposing sidewalls.
16. The device of claim 15 , wherein the gate extends laterally over the semiconductor substrate outside of the active area.