Backside coupling with superconducting partial TSV for transmon qubits
A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.
1. A capacitive coupling device (superconducting C-coupler) comprising:
a trench through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate;
a superconducting material deposited as a via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside;
a superconducting pad on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside; and
an extension of the via layer on the backside, wherein the extension couples to a quantum readout circuit element fabricated on the backside.
2. The superconducting C-coupler of claim 1 , further comprising:
a dielectric material filled, from the backside, in the space between the surfaces of the via layer.
3. The superconducting C-coupler of claim 2 , wherein the dielectric material is Silicon oxide (SiO2).
4. The superconducting C-coupler of claim 2 ,
wherein the dielectric material is etched such that the dielectric material is removed and the space is occupied by air.
5. The superconducting C-coupler of claim 1 ,
wherein a layer of a second superconducting material is deposited on the frontside, and
wherein the layer of the second superconducting material is masked and etched to form the superconducting pad on the frontside.
6. The superconducting C-coupler of claim 5 ,
wherein the layer of the second superconducting material is deposited prior to forming the trench, and
wherein the layer of the second superconducting material is protected by a sacrificial layer.
7. The superconducting C-coupler of claim 1 , wherein the extension of the via layer is electrically coupled with the quantum readout circuit element.
8. The superconducting C-coupler of claim 1 , wherein the extension of the via layer is directly electrically coupled with the quantum readout circuit element.
9. The superconducting C-coupler of claim 1 ,
wherein the extension of the via layer is electrically coupled to a second superconducting pad on the backside, and
wherein the second superconducting pad couples with the quantum readout circuit element.
10. The superconducting C-coupler of claim 1 ,
wherein the quantum readout circuit element comprises a ground-plane of a circuit, and
wherein the C-coupler additionally functions as a grounding shield for other C-couplers coupling with the circuit.
11. A method comprising:
forming, in a capacitive coupling device (superconducting C-coupler), a trench through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate;
depositing a superconducting material as a via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside;
forming a superconducting pad on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside; and
forming an extension of the via layer on the backside, wherein the extension couples to a quantum readout circuit element fabricated on the backside.
12. The method of claim 11 , further comprising:
filling a dielectric material, from the backside, in the space between the surfaces of the via layer.
13. The method of claim 12 , wherein the dielectric material is Silicon oxide (SiO2).
14. The method of claim 12 ,
wherein the dielectric material is etched such that the dielectric material is removed and the space is occupied by air.
15. The method of claim 11 , further comprising:
depositing a layer of a second superconducting material on the frontside; and
masking and etching the layer of the second superconducting material to form the superconducting pad on the frontside.
16. The method of claim 15 , further comprising:
depositing the layer of the second superconducting material prior to forming the trench; and
protecting, using a sacrificial layer, the layer of the second superconducting material.
17. The method of claim 11 , further comprising:
electrically coupling the extension of the via layer with the quantum readout circuit element.
18. The method of claim 11 , further comprising:
directly electrically coupling the extension of the via layer with the quantum readout circuit element.
19. The method of claim 11 , further comprising:
electrically coupling the extension of the via layer to a second superconducting pad on the backside, wherein the second superconducting pad couples with the quantum readout circuit element.
20. The method of claim 11 ,
wherein the quantum readout circuit element comprises a ground-plane of a circuit, and
wherein the C-coupler additionally functions as a grounding shield for other C-couplers coupling with the circuit.