IP Library › Granted Patent US 12,532,670
Granted Patent B2
US 12,532,670 · App. 17/545,985 · Granted Jan 20, 2026

Vertical transmon structure and its fabrication process

Inventors: Masao Tokunari (Yokohama, JP); Naoki Kanazawa (Yokohama, JP); Akihiro Horibe (Yokohama, JP); Kuniaki Sueoka (Sagamihara, JP)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H10N60/0688G06N10/00H10N60/0912
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,532,670
App. No.
17/545,985
Granted
Jan 20, 2026
Kind
B2
Abstract

A vertical transmon qubit structure, includes a substrate having a first surface and a second surface. A through-silicon-via (TSV) is located in the substrate. A first electrode of a Josephson junction (JJ) is located on a portion of the first surface of the substrate and adjacent to the TSV. A second electrode of the JJ is in contact with the TSV and on a second portion of the first surface of the substrate. The first electrode is separated from the second electrode by an insulator.

Claims (37)

1 . A method of fabricating vertical transmon qubit structure, comprising:

providing a substrate having a top surface and a bottom surface;

providing a first layer of aluminum (Al) on the bottom surface the substrate;

providing a first photoresist layer on portions of the bottom surface of the substrate and the first layer of Al;

providing a first layer of niobium (Nb) on a bottom side of the substrate;

providing a second photoresist layer on the top surface of the substrate with an opening in a center portion of the substrate;

creating a through silicon via (TSV) in the center portion of the substrate by way of etching the substrate in the center portion of the substrate;

depositing a second layer of Al within the TSV;

removing portions of the second photoresist layer;

depositing a second layer of Nb on a top side of the substrate; and

removing the first Nb layer below the first resist layer and the second Nb layer above the second resist layer as well the first and second resist layers.

2 . The method of claim 1 , wherein the substrate is silicon (Si).

3 . The method of claim 1 , wherein the layer of aluminum on the bottom surface of the substrate has a vertical width of 50 nm and a thickness of 200 nm.

4 . The method of claim 1 , further comprising removing a natural oxide on the first layer of Al before providing the first layer of Nb on the bottom side of the substrate.

5 . The method of claim 1 , wherein a parallel plate capacitance between the first Nb layer and the second Nb layer is 50 fF.

6 . The method of claim 1 , further comprising removing a natural oxide on the second layer of Al before providing the second layer of Nb.

7 . The method of claim 1 , wherein either the first Nb layer or the second Nb layer is capacitively coupled to a vertical resonator.

8 . A method of fabricating vertical transmon qubit structure, comprising:

providing a substrate having a top surface and a bottom surface;

providing a first layer of aluminum (Al) on the bottom surface the substrate;

providing a first photoresist layer on portions of the bottom surface of the substrate and the first layer of Al;

providing a second photoresist layer on the top surface of the substrate with an opening in a center portion of the substrate;

providing a first layer of niobium (Nb) on a bottom side of the substrate;

creating a through silicon via (TSV) in the center portion of the substrate by way of etching the substrate in the center portion of the substrate;

providing a self-assembled monolayer (SAM) of a third photoresist layer on the bottom side and a top side of the substrate but not in a middle portion of the first photoresist layer;

depositing a second layer of Al within a base of the TSV;

removing the third photoresist layer;

depositing a second layer of Nb on a top side of the substrate; and

removing the first Nb layer below the first resist layer and the second Nb layer above the second resist layer as well the first and second resist layers.

9 . The method of claim 8 , wherein the deposition of the second layer of aluminum (Al) is by way of a selective atomic layer deposition (ALD).

10 . The method of claim 8 , wherein the substrate is silicon (Si).

11 . The method of claim 8 , wherein the layer of aluminum on the bottom surface of the substrate has a vertical width of 50 nm and a thickness of 200 nm.

12 . The method of claim 8 , further comprising removing a natural oxide on the first layer of Al before providing the first layer of Nb on the bottom side of the substrate.

13 . The method of claim 8 , wherein a parallel plate capacitance between the first Nb layer and the second Nb layer is 50 fF.

14 . The method of claim 8 , further comprising removing a natural oxide on the second layer of Al before providing the second layer of Nb.

15 . The method of claim 8 , wherein either the first Nb layer or the second Nb layer is capacitively coupled to a vertical resonator.

16 . The method of claim 8 , further comprising providing an insulator layer between the first layer of Al and the second layer of Al comprising aluminum oxide (Al 2 O 3 ).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2021
From: TOKUNARI, MASAO; KANAZAWA, NAOKI; HORIBE, AKIHIRO; SUEOKA, KUNIAKI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 058341/0254 →
Continuity (1)
Related Publication 20230180630A1 · Jun 8, 2023
References Cited (10)
US 9177814B2 · Chang et al. · 2015 [cited by applicant]
US 9524470B1 · Chow et al. · 2016 [cited by applicant]
US 10235635B1 · Abdo · 2019 [cited by applicant]
US 10256392B1 · Brink et al. · 2019 [cited by applicant]
US 10446736B2 · Hertzberg et al. · 2019 [cited by applicant]
US 10497746B1 · Rosenblatt et al. · 2019 [cited by applicant]
US 10615223B2 · Rosenblatt et al. · 2020 [cited by applicant]
US 10840428B2 · Kanazawa et al. · 2020 [cited by applicant]
US 11276727B1 · Renzas · 2022 [cited by examiner]
US 20200287117A1 · Kanazawa et al. · 2020 [cited by applicant]