Methods of forming replacement gate structures on transistor devices

1. A method, comprising:

forming a sacrificial gate structure above a semiconductor substrate, said sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material;

performing a first gate-cut etching process to thereby form an opening in said sacrificial gate electrode material, wherein said opening laterally separates an upper portion of said sacrificial gate electrode material into a first upper sacrificial gate electrode portion and a second upper sacrificial gate electrode portion, said opening exposing a first end surface of said first upper sacrificial gate electrode portion and a second end surface of said second upper sacrificial gate electrode portion;

after forming said opening, forming an internal sidewall spacer in said opening so as to cover said exposed first and second end surfaces;

after forming said internal sidewall spacer, performing a second gate-cut etching process through said opening, said second gate-cut etching process being adapted to remove said sacrificial gate electrode material;

performing an oxidizing anneal process; and

forming an insulating material in at least said opening.

2. The method of claim 1 , wherein performing said first gate-cut etching process comprises performing said first gate-cut etching process to thereby form said opening with a bottom that stops within said sacrificial gate electrode material and said second gate-cut etching process stops on said sacrificial gate insulation layer and removes said sacrificial gate electrode material at said bottom of said opening.

3. The method of claim 1 , wherein forming said internal sidewall spacer comprises forming said internal sidewall spacer such that a portion of said sacrificial gate electrode material is positioned vertically below said internal sidewall spacer.

4. The method of claim 3 , wherein said oxidizing anneal process converts at least said portion of said sacrificial gate electrode material positioned vertically below said internal sidewall spacer into a region of silicon dioxide.

5. The method of claim 1 , wherein performing said oxidizing anneal process comprises performing a steam anneal process.

6. The method of claim 1 , wherein said insulating material in at least said opening and said internal sidewall spacer at least partially define an insulating gate separation structure.

7. The method of claim 6 , further comprising:

removing materials of said sacrificial gate structure on opposite sides of said insulating gate separation structure to form first and second replacement gate cavities on opposite sides of said insulating gate separation structure; and

forming first and second replacement gate structures in said first and second replacement gate cavities, respectively.

8. The method of claim 7 , wherein said first and second replacement gate structures comprise a high-k replacement gate insulation layer and a replacement gate electrode that comprises at least one metal-containing layer of material.

9. The method of claim 1 , wherein said sacrificial gate structure is formed for one of a FinFET device, a planar transistor device or a vertical transistor device, wherein said sacrificial gate insulation layer comprises silicon dioxide and wherein said sacrificial gate electrode material comprises one of polysilicon or amorphous silicon.

10. The method of claim 9 , wherein said first gate-cut etching process and said second gate-cut etching process are performed with at least one halogen-based material as an etchant material.

11. The method of claim 1 , wherein said insulating material in at least said opening and said internal sidewall spacer are both comprised of a same insulating material.

12. The method of claim 1 , further comprising forming a sidewall spacer adjacent to sidewalls of said sacrificial gate structure prior to forming said opening in said sacrificial gate electrode material.

13. The method of claim 1 , wherein said second gate-cut etching process exposes a sidewall surface of a lower portion of said sacrificial gate electrode material positioned below said upper portion of said sacrificial gate electrode material, and wherein said exposed sidewall surface of said lower portion of said sacrificial gate electrode material is exposed to said oxidizing anneal process.

14. A method, comprising:

forming a continuous line-type sacrificial gate structure above a semiconductor substrate, said sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material;

performing a first gate-cut etching process to thereby form an opening in said sacrificial gate electrode material, said opening having a bottom that stops within said sacrificial gate electrode material, wherein said opening laterally separates an upper portion of said sacrificial gate electrode material into a first upper sacrificial gate electrode portion and a second upper sacrificial gate electrode portion, exposes a first end surface of said first upper sacrificial gate electrode portion, and exposes a second end surface of said second upper sacrificial gate electrode portion;

after forming said opening, forming an internal sidewall spacer in said opening so as to cover said exposed first and second end surfaces and such that a lower portion of said sacrificial gate electrode material is positioned vertically below said internal sidewall spacer;

after forming said internal sidewall spacer, performing a second gate-cut etching process that stops on said sacrificial gate insulation layer and removes said sacrificial gate electrode material at said bottom of said opening;

performing an oxidizing anneal process to convert at least said portion of said sacrificial gate electrode material positioned vertically below said internal sidewall spacer into a region of silicon dioxide; and

forming an insulating material in at least said opening.

15. The method of claim 14 , wherein performing said oxidizing anneal process comprises performing a steam anneal process.

16. The method of claim 14 , wherein said insulating material in at least said opening and said internal sidewall spacer at least partially define an insulating gate separation structure.

17. The method of claim 16 , further comprising:

removing materials of said sacrificial gate structure on opposite sides of said insulating gate separation structure to form first and second replacement gate cavities on opposite sides of said insulating gate separation structure; and

forming first and second replacement gate structures in said first and second replacement gate cavities, respectively.

18. The method of claim 14 , further comprising forming a sidewall spacer adjacent to sidewalls of said continuous line-type sacrificial gate structure prior to forming said opening in said sacrificial gate electrode material.

19. The method of claim 14 , wherein said second gate-cut etching process exposes a sidewall surface of said lower portion of said sacrificial gate electrode material positioned vertically below said internal sidewall spacer, and wherein said exposed sidewall surface of said lower portion of said sacrificial gate electrode material is exposed to said oxidizing anneal process.

20. A method, comprising:

forming a sacrificial gate structure above a semiconductor substrate, said sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material;

forming a sidewall spacer adjacent to sidewalls of said sacrificial gate structure;

after forming said sidewall spacer, performing a first gate-cut etching process to thereby form an opening that extends through an upper portion of said sacrificial gate electrode material and laterally separates said upper portion into a first upper sacrificial gate electrode portion and a second upper sacrificial gate electrode portion, said opening exposing a first end surface of said first upper sacrificial gate electrode portion of said sacrificial gate electrode material and exposing a second end surface of said second upper sacrificial gate electrode portion of said sacrificial gate electrode material;

after forming said opening, forming an internal sidewall spacer in said opening, said internal sidewall spacer covering said exposed first and second end surfaces of said respective first and second upper sacrificial gate electrode portions;

after forming said internal sidewall spacer, performing a second gate-cut etching process through said opening so as to extend said opening through a remaining lower portion of said sacrificial gate electrode material and expose said sacrificial gate insulation material positioned therebelow, said extended opening exposing sidewall surfaces of said remaining lower portion;

performing an oxidation process on said exposed sidewall surfaces of said remaining lower portion so as to convert part of said remaining lower portion into an insulating material;

forming an insulating material in said extended opening, said insulating material and said internal sidewall spacer at least partially defining an insulating gate separation structure;

removing materials of said sacrificial gate structure on opposite sides of said insulating gate separation structure to form first and second replacement gate cavities on opposite sides of said insulating gate separation structure; and

forming first and second replacement gate structures in said first and second replacement gate cavities, respectively.