Semiconductor device and memory system
A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.
1. A semiconductor device configured to communicate with a controller, the semiconductor device comprising:
a first chip that includes a first circuit having a first output terminal; and
a second chip that includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line,
wherein when the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal, and the second chip transmits to the controller a signal indicating that the second chip is in a busy state upon starting the first calibration operation, and transmits to the controller a signal indicating that the second chip is in a ready state upon completion of the first calibration operation.
2. The semiconductor device according to claim 1 ,
wherein the first circuit includes a first pull-up circuit having a first terminal to which a first voltage is supplied and a second terminal electrically connected to the first output terminal, and a first pull-down circuit having a first terminal to which a second voltage smaller than the first voltage is supplied and a second terminal electrically connected to the first output terminal, and
the second circuit includes a second pull-up circuit having a first terminal to which the first voltage is supplied and a second terminal electrically connected to the second output terminal, a second pull-down circuit having a first terminal to which the second voltage is supplied and a second terminal electrically connected to the second output terminal, and a comparator having a first input terminal to which a voltage of the second output terminal is supplied and a second input terminal to which a third voltage between the first voltage and the second voltage is supplied.
3. The semiconductor device according to claim 2 , wherein the first calibration operation includes
a first operation during which the first pull-up circuit and the second pull-down circuit enter an ON state while the first pull-down circuit and the second pull-up circuit enter an OFF state, and
a second operation during which the second pull-up circuit and the first pull-down circuit enter an ON state while the second pull-down circuit and the first pull-up circuit enter an OFF state.
4. The semiconductor device according to claim 3 , wherein
during the first operation, the second circuit calibrates a resistance value of the second pull-down circuit based on a comparison result of the comparator that compares the voltage of the second output terminal with the third voltage.
5. The semiconductor device according to claim 3 , wherein
during the second operation, the second circuit calibrates a resistance value of the second pull-up circuit based on a comparison result of the comparator that compares the voltage of the second output terminal with the third voltage.
6. The semiconductor device according to claim 3 ,
wherein the second pull-up circuit includes a first transistor and a second transistor which are connected in parallel between a voltage supply supplying the first voltage and the second output terminal, and
the first transistor and the second transistor have different resistance values in an ON state.
7. The semiconductor device according to claim 3 ,
wherein the second pull-down circuit includes a third transistor and a fourth transistor which are connected in parallel between a voltage supply supplying the second voltage and the second output terminal, and
the third transistor and the fourth transistor have different resistance values in an ON state.
8. The semiconductor device according to claim 1 , further comprising:
a third chip that includes a third circuit having a third output terminal, which is electrically connected to a fourth output terminal, which is located in the first chip, via a second signal line, and
when the first chip and the third chip receive the first command, the third circuit calibrates an output impedance at the third output terminal through a second calibration operation based on an output impedance at the fourth output terminal.
9. The semiconductor device according to claim 8 ,
wherein the first calibration operation and the second calibration operation are performed in parallel.
10. The semiconductor device according to claim 8 ,
wherein the first calibration operation and the second calibration operation are performed in series.
11. The semiconductor device according to claim 1 ,
wherein the first command identifies the first chip.
12. The semiconductor device according to claim 1 ,
wherein the output impedance at the first output terminal is calibrated prior to the first calibration operation.
13. The semiconductor device according to claim 1 , wherein
the first chip generates calibration result information based on calibration results of the output impedance at the first output terminal and
the first calibration operation includes adjusting the output impedance of the second output terminal based on the calibration result information.
14. The semiconductor device according to claim 13 , wherein
the first circuit includes a first pull-up circuit having a first terminal to which a first voltage is supplied and a second terminal electrically connected to the first output terminal, and a first pull-down circuit having a first terminal to which a second voltage smaller than the first voltage is supplied and a second terminal electrically connected to the first output terminal, and
the calibration result information includes a first information corresponding to a resistance value of the first pull-up circuit, and a second information corresponding to a resistance value of the first pull-down circuit.
15. The semiconductor device according to claim 14 , wherein
the second circuit includes a second pull-up circuit having a first terminal to which the first voltage is supplied and a second terminal electrically connected to the second output terminal and a second pull-down circuit having a first terminal to which the second voltage is supplied and a second terminal electrically connected to the second output terminal, and
a resistance value of the second pull-up circuit is set based on the first information, and a resistance value of the second pull-down circuit is set based on the second information.
16. The semiconductor device according to claim 15 ,
wherein the first information and the second information include a digital-to-analog converter (DAC) value.
17. A memory system comprising:
a semiconductor device including a first chip that includes a first circuit having a first output terminal, a second chip that includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line; and
a controller that is electrically connected to the first chip and the second chip via the first signal line, and issues a first command, wherein
when the first chip and the second chip receive the first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal and the second chip transmits to the controller a signal indicating that the second chip is in a busy state upon starting the first calibration operation, and transmits to the controller a signal indicating that the second chip is in a ready state upon completion of the first calibration operation.
18. The memory system according to claim 17 , wherein
the first chip generates calibration result information based on calibration results of the output impedance at the first output terminal, and
the first calibration operation includes adjusting the output impedance of the second output terminal based on the calibration result information.
19. The memory system according to claim 18 ,
wherein the calibration result information is transmitted from the first chip to the controller and then from the controller to the second chip.
20. The memory system according to claim 19 , wherein
the semiconductor device further includes a third chip having a third circuit having a third output terminal, which is electrically connected to the first chip via a second signal line, and
the calibration result information transmitted from the first chip to the controller is also transmitted from the controller to the third chip and the third chip performs a second calibration operation to adjust the output impedance of the third output terminal based on the calibration result information.
21. The semiconductor device according to claim 1 , wherein
after receiving the first command, the first calibration operation is carried out without any control from the controller.
22. The semiconductor device according to claim 1 , wherein
the first chip carries out a calibration before the first calibration operation, and
a duration required for the calibration carried out by the first chip is longer than a duration required for the first calibration operation.
23. The semiconductor device according to claim 1 , wherein
during the first calibration operation the first chip transmits a signal indicating that the first chip is in a ready state.