Display device and method of manufacturing the same

1. A display device comprising:

a substrate;

a buffer layer disposed on the substrate;

a first semiconductor layer of a first thin film transistor disposed on the buffer layer;

a gate insulating layer disposed on a channel region of the first semiconductor layer, on a source region of the first semiconductor layer, and on a drain region of the first semiconductor layer;

a first gate electrode disposed on the gate insulating layer over the channel region of the first semiconductor layer;

a first source electrode in direct contact with the source region of the first semiconductor layer, wherein the first source electrode is disposed on the gate insulating layer over the source region of the first semiconductor layer and contacts the source region of the first semiconductor layer via a first channel hole through the gate insulating layer;

a first drain electrode in direct contact with the drain region of the first semiconductor layer, wherein the first drain electrode is disposed on the gate insulating layer over the drain region of the first semiconductor layer and contacts the drain region of the first semiconductor layer via a second channel hole through the gate insulating layer;

a passivation layer disposed on the first gate electrode, the first source electrode, and the first drain electrode, wherein the passivation layer is in direct contact with the first semiconductor layer in a region between the first source electrode and the first gate electrode, and wherein the passivation layer is in direct contact with the first semiconductor layer in a region between the first gate electrode and the first drain electrode,

wherein the first gate electrode, the first source electrode, and the first drain electrode are in a same layer and comprise a same material.

2. The display device of claim 1 , further comprising:

a second semiconductor layer of a second thin film transistor disposed on the buffer layer;

wherein the gate insulating layer is further disposed on a channel region of the second semiconductor layer;

a second gate electrode disposed on the gate insulating layer over the channel region of the second semiconductor layer;

a second source electrode in direct contact with a source region of the second semiconductor;

a second drain electrode in direct contact with a drain region of the second semiconductor layer;

wherein the passivation layer is further disposed on the second gate electrode, the second source electrode, and the second drain electrode, wherein the passivation layer is in direct contact with second semiconductor layer in a region between the second source electrode and the second gate electrode, and wherein the passivation layer is in direct contact with the second semiconductor layer in a region between the second gate electrode and the second drain electrode,

wherein the second gate electrode, the second drain electrode, and the second source electrode are in the same layer and comprise the same material as the first gate electrode, the first source electrode, and the first drain electrode.

3. The display device of claim 1 ,

wherein the buffer layer is in direct contact with the substrate,

wherein first semiconductor layer is in direct contact with the buffer layer,

wherein the gate insulating layer is in direct contact with the first semiconductor layer,

wherein the first gate electrode is in direct contact with the gate insulating layer, and

wherein the passivation layer is in direct contact with the first gate electrode, the first source electrode, and the first drain electrode.

4. The display device of claim 1 , further comprising:

a data line disposed on the substrate, wherein the buffer layer is further disposed on the data line;

a second semiconductor layer disposed on the buffer layer; and

a gate pattern disposed over the buffer layer and in direct contact with the second semiconductor layer, the gate pattern in direct contact with the data line via a hole through the buffer layer.

5. The display device of claim 4 , wherein the gate insulating layer is disposed on the first semiconductor layer only on the channel region of the first semiconductor layer and is not disposed on the source region or the drain region of the first semiconductor layer.

6. The display device of claim 5 ,

wherein the first drain electrode is in direct contact with the drain region of the first semiconductor layer in an entire overlapping region of the first drain electrode and the drain region of the first semiconductor layer; and

wherein the first source electrode is in direct contact with the source region of the first semiconductor layer in an entire overlapping region of the first source electrode and the source region of the first semiconductor layer.

7. The display device of claim 4 ,

wherein the gate insulating layer is further disposed on the second semiconductor layer and the buffer layer;

wherein the gate pattern is disposed on the gate insulating layer; and

wherein the hole through the buffer layer is further through the gate insulating layer.

8. The display device of claim 1 , further comprising:

a light shielding layer disposed on the substrate, wherein the buffer layer is further disposed on the light shielding layer;

a second semiconductor layer disposed on the buffer layer over the light shielding layer;

wherein the passivation layer is further in direct contact with the second semiconductor layer over the light shielding layer; and

a pixel electrode disposed on the passivation layer over the light shielding layer.

9. The display device of claim 8 , wherein the light shielding layer is in direct contact with the first source electrode.

10. The display device of claim 1 , wherein the display device comprises an organic light emitting diode (OLED) device.

11. A display device comprising:

a substrate;

a buffer layer disposed on the substrate;

a first semiconductor layer of a first thin film transistor disposed on the buffer layer;

a gate insulating layer disposed on a channel region of the first semiconductor layer;

a first gate electrode disposed on the gate insulating layer over the channel region of the first semiconductor layer;

a first source electrode in direct contact with a source region of the first semiconductor layer;

a first drain electrode in direct contact with a drain region of the first semiconductor layer;

wherein the first gate electrode, the first source electrode, and the first drain electrode are in a same layer and comprise a same material;

a passivation layer disposed on the first gate electrode, the first source electrode, and the first drain electrode, wherein the passivation layer is in direct contact with the first semiconductor layer in a region between the first source electrode and the first gate electrode, and wherein the passivation layer is in direct contact with the first semiconductor layer in a region between the first gate electrode and the first drain electrode;

a data line disposed on the substrate, wherein the buffer layer is further disposed on the data line;

a second semiconductor layer disposed on the buffer layer; and

a gate pattern disposed over the buffer layer and in direct contact with the second semiconductor layer, the gate pattern in direct contact with the data line via a hole through the buffer layer.

12. The display device of claim 11 ,

wherein the gate pattern is in direct contact with the second semiconductor layer and the buffer layer in an entire overlapping region of the gate pattern and the second semiconductor layer.

13. The display device of claim 11 , wherein the second semiconductor layer is disposed on the buffer layer without overlapping the data line.

14. The display device of claim 11 , wherein the second semiconductor layer is disposed on the buffer layer at least partially overlapping the data line.

15. The display device of claim 11 , further comprising:

a third semiconductor layer of a second thin film transistor disposed on the buffer layer;

wherein the gate insulating layer is further disposed on a channel region of the third semiconductor layer;

a second gate electrode disposed on the gate insulating layer over the channel region of the third semiconductor layer;

a second source electrode in direct contact with a source region of the second semiconductor;

a second drain electrode in direct contact with a drain region of the third semiconductor layer;

wherein the passivation layer is further disposed on the second gate electrode, the second source electrode, and the second drain electrode, wherein the passivation layer is in direct contact with second semiconductor layer in a region between the second source electrode and the second gate electrode, and wherein the passivation layer is in direct contact with the second semiconductor layer in a region between the second gate electrode and the second drain electrode,

wherein the second gate electrode, the second drain electrode, and the second source electrode are in the same layer and comprise the same material as the first gate electrode, the first source electrode, and the first drain electrode.

16. The display device of claim 11 ,

wherein the buffer layer is in direct contact with the substrate,

wherein first semiconductor layer is in direct contact with the buffer layer,

wherein the gate insulating layer is in direct contact with the first semiconductor layer,

wherein the first gate electrode is in direct contact with the gate insulating layer, and

wherein the passivation layer is in direct contact with the first gate electrode, the first source electrode, and the first drain electrode.

17. The display device of claim 11 ,

wherein the gate insulating layer is further disposed on a source region of the first semiconductor layer and on a drain region of the first semiconductor layer;

wherein the first source electrode is disposed on the gate insulating layer over the source region of the first semiconductor layer and contacts the source region of the first semiconductor layer via a first channel hole through the gate insulating layer; and

wherein the first drain electrode is disposed on the gate insulating layer over the drain region of the first semiconductor layer and contacts the drain region of the first semiconductor layer via a second channel hole through the gate insulating layer.

18. The display device of claim 11 , further comprising:

a light shielding layer disposed on the substrate, wherein the buffer layer is further disposed on the light shielding layer;

a third semiconductor layer disposed on the buffer layer over the light shielding layer;

wherein the passivation layer is further in direct contact with the third semiconductor layer over the light shielding layer; and

a pixel electrode disposed on the passivation layer over the light shielding layer.

19. The display device of claim 11 , wherein the display device comprises an organic light emitting diode (OLED) device.

20. The display device of claim 11 ,

wherein the gate insulating layer is further disposed on the second semiconductor layer and the buffer layer;

wherein the gate pattern is disposed on the gate insulating layer; and

wherein the hole through the buffer layer is further through the gate insulating layer.