Display panel and method of manufacturing the same
A display panel includes a base substrate, a transistor disposed on the base substrate and including a semiconductor pattern including a source area, a drain area, and an active area, a gate insulating pattern layer disposed on the semiconductor pattern, and a gate electrode disposed on the gate insulating pattern, and connection electrodes disposed on the gate insulating pattern layer and connected to the semiconductor pattern through contact holes, respectively. The gate insulating pattern layer includes a first portion overlapping at least one of the source area and the drain area and a second portion extending from the first portion. A thickness of the first portion is equal to or smaller than about 50% of a thickness of the second portion.
1 . A display panel comprising:
a base substrate;
a transistor disposed on the base substrate and comprising a semiconductor pattern including a source area, a drain area, and an active area, a gate insulating pattern layer disposed on the semiconductor pattern, and a gate electrode disposed on the gate insulating pattern layer; and
connection electrodes disposed on the gate insulating pattern layer and connected to the semiconductor pattern through contact holes, respectively,
wherein the gate insulating pattern layer comprising:
a first portion overlapping at least one of the source area and the drain area and having a first thickness; and
a second portion extending from the first portion and having a second thickness,
wherein the first thickness of the first portion is equal to or smaller than the second thickness of the second portion, and
wherein the first portion is separated from a portion of the gate insulating pattern layer disposed between the gate electrode and the active area, and the portion of the gate insulating pattern layer has the second thickness equal to or greater than the first thickness of the first portion.
2 . The display panel of claim 1 , wherein the first portion is in contact with at least one of the source area and the drain area.
3 . The display panel of claim 2 , wherein the first thickness of the first portion is equal to or smaller than about 500 angstroms and is greater than zero.
4 . The display panel of claim 1 , wherein the second portion extends from the first portion to a first direction in a plan view and a width of the first portion in the first direction is equal to or greater than about 0.2 micrometers and is smaller than a width of each of the contact holes.
5 . The display panel of claim 1 , wherein the connection electrodes comprise:
a first connection electrode connected to the drain area; and
a second connection electrode connected to the source area, and
wherein the first connection electrode and the second connection electrode are disposed on a same layer as a layer on which the gate electrode is disposed.
6 . The display panel of claim 5 , wherein each of the first connection electrode and the second connection electrode includes a same material as the gate electrode.
7 . The display panel of claim 5 , further comprising a first conductive pattern and a second conductive pattern disposed between the base substrate and the transistor and spaced apart from each other in a plan view,
wherein the first conductive pattern is electrically connected to the drain area via the first connection electrode and the second conductive pattern is electrically connected to the source area via the second connection electrode.
8 . The display panel of claim 7 , wherein the gate insulating pattern layer comprises a first insulating pattern, a second insulating pattern, and a third insulating pattern spaced apart from each other in a plan view,
wherein the first insulating pattern is disposed between the first connection electrode and the semiconductor pattern, the second insulating pattern is disposed between the gate electrode and the semiconductor pattern, and the third insulating pattern is disposed between the second connection electrode and the semiconductor pattern.
9 . The display panel of claim 7 , wherein the first conductive pattern overlaps the semiconductor pattern in a plan view.
10 . The display panel of claim 8 , wherein the first connection electrode is connected to the first conductive pattern via a first contact hole defined through the first insulating pattern,
wherein the first insulating pattern comprises:
a first portion disposed adjacent to the first contact hole; and
a second portion extending from the first portion of the first insulating pattern, and
wherein a thickness of the first portion of the first insulating pattern is equal to or smaller than a thickness of the second portion of the first insulating pattern.
11 . The display panel of claim 10 , further comprising a buffer layer disposed between the gate insulating pattern layer and the first and second conductive patterns, wherein the first contact hole is defined through the buffer layer and the first insulating pattern.
12 . The display panel of claim 11 , wherein a side surface of the second portion of the first insulating pattern connected to the first portion of the first insulating pattern is disposed on the buffer layer.
13 . The display panel of claim 5 , further comprising a light emitting element disposed on the first connection electrode and the second connection electrode,
wherein the light emitting element comprising a first electrode electrically connected to the transistor via the first connection electrode, a light emitting layer, and a second electrode.
14 . The display panel of claim 1 , wherein at least one of the source area and the drain area includes a hole, and the hole is adjacent to the first portion.
15 . A method of manufacturing a display panel, comprising:
providing a base substrate on which conductive patterns and a preliminary semiconductor pattern are formed;
forming a gate insulating layer on the preliminary semiconductor pattern;
forming contact holes through the gate insulating layer; and
forming a connection electrode and a gate electrode on the gate insulating layer,
wherein a first portion of the gate insulating layer disposed adjacent to the contact holes and a second portion of the gate insulating layer extending from the first portion are formed through the forming of the contact holes, and
wherein a first thickness of the first portion is equal to or smaller than a second thickness of the second portion.
16 . The method of claim 15 , wherein the forming of the contact holes comprises:
forming a photoresist layer on the gate insulating layer, the photoresist layer including openings;
first etching the gate insulating layer to form the contact holes through the gate insulating layer to overlap the openings;
ashing the photoresist layer to expand a size of each of the openings such that a portion of an upper surface of the gate insulating layer adjacent to the contact holes is exposed; and
second etching the gate insulating layer to form the first portion of the gate insulating layer by partially etching the gate insulating layer.
17 . The method of claim 16 , wherein each of the first etching and the second etching is performed by a dry etching process.
18 . The method of claim 16 , wherein the first etching is performed using a gas comprising tetrafluoromethane (CF4) and argon (Ar).
19 . The method of claim 16 , wherein the second etching is performed using a gas comprising nitrogen trifluoride (NF3) and oxygen (O2).
20 . The method of claim 16 , wherein the ashing is performed using a gas comprising oxygen (O2).