Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions
Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.
1. An integrated circuit structure, comprising:
a semiconductor fin above and continuous with a semiconductor substrate, the semiconductor fin comprising a channel region having an uppermost surface;
an isolation structure above the semiconductor substrate and adjacent to lower portions of the semiconductor fin, wherein an upper portion of the semiconductor fin protrudes above an uppermost surface of the isolation structure;
epitaxial source or drain regions adjacent to the channel region in the upper portion of the semiconductor fin, wherein the epitaxial source or drain regions have substantially vertical sidewalls, and wherein the epitaxial source and drain regions do not extend laterally over the isolation structure, wherein the epitaxial source and drain regions have an uppermost surface above the uppermost surface of the channel of the semiconductor fin, and wherein the epitaxial source or drain regions have a bottom surface below the uppermost surface of the isolation structure; and
a gate electrode over the channel region of the semiconductor fin.
2. The integrated circuit structure of claim 1 , wherein the epitaxial source or drain regions are stress inducing for the channel region.
3. The integrated circuit structure of claim 1 , further comprising:
a contact metal layer disposed on all surfaces of the epitaxial source or drain regions exposed above the uppermost surface of the isolation structure.
4. The integrated circuit structure of claim 1 , wherein the epitaxial source or drain regions comprise a semiconductor material different than a semiconductor material of the channel region of the semiconductor fin.
5. The integrated circuit structure of claim 1 , wherein the epitaxial source or drain regions have a bottom surface below the uppermost surface of the isolation structure.
6. The integrated circuit structure of claim 1 , wherein the epitaxial source or drain regions have a bottom surface approximately planar with the uppermost surface of the isolation structure.
7. The integrated circuit structure of claim 1 , wherein the epitaxial source or drain regions have a bottom surface above the uppermost surface of the isolation structure.