Transistor fins with different thickness gate dielectric
First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.
1. An integrated circuit device comprising:
a first fin-type field effect transistor (finFET) and a second finFET laterally adjacent one another extending from a surface of an isolation layer, wherein the first finFET has a first fin structure and the second finFET has a second fin structure;
an insulator layer on the first fin structure and the second fin structure;
a gate conductor intersecting the first fin structure and the second fin structure, wherein at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure; and
source and drain structures on the first fin structure and the second fin structure laterally adjacent the gate conductor,
wherein the first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step, and
wherein the step is approximately parallel to the surface of the isolation layer.
2. The integrated circuit device in claim 1 , wherein a portion of the first fin structure extending from the isolation layer is thinner relative to a portion of the second fin structure extending from the isolation layer.
3. The integrated circuit device in claim 1 , further comprising:
a plurality of the first fin structure comprising first fin structures; and
a plurality of the second fin structure comprising second fin structures,
where a first distance between adjacent ones of the first fin structures is greater than a second distance between adjacent ones of the second fin structures.
4. The integrated circuit device in claim 1 , wherein the insulator layer comprises a first portion on the first fin structure and a second portion on the second fin structure, and wherein the first portion of the insulator layer is thicker than the second portion of the insulator layer.
5. The integrated circuit device in claim 1 , wherein the insulator layer comprises a first portion on the first fin structure and a second portion on the second fin structure,
wherein the first portion of the insulator layer comprises at least two layers of different insulating materials, and
wherein the second portion of the insulator layer comprises relatively less layers of insulating materials relative to the first portion of the insulator layer.
6. The integrated circuit device in claim 5 , wherein the at least two layers of different insulating materials comprise an oxide layer and a high-k insulator layer, and wherein the relatively less layers comprises only the high-k insulator layer.
7. An integrated circuit device comprising:
a first fin-type field effect transistor (finFET) and a second finFET laterally adjacent one another extending from a surface of an isolation layer, wherein the first finFET has a first fin structure and the second finFET has a second fin structure;
an insulator layer on the first fin structure and the second fin structure;
a gate conductor intersecting the first fin structure and the second fin structure, wherein at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure;
a work function metal layer between the gate conductor and the insulator layer; and
source and drain structures on the first fin structure and the second fin structure laterally adjacent the gate conductor,
wherein the first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step, and
wherein the step is approximately parallel to the surface of the isolation layer.
8. An integrated circuit device comprising:
a substrate;
an isolation layer on the substrate, wherein the isolation layer has a surface opposite where the isolation layer contacts the substrate, and wherein the isolation layer has a first area separated from a second area;
first fin-type field effect transistors (finFETs) in the first area of the isolation layer, wherein the first finFETs have first fin structures extending from the substrate through the isolation layer and extending external to the isolation layer;
second finFETs in the second area of the isolation layer, wherein the second finFETs have second fin structures extending from the substrate through the isolation layer and extending external to the isolation layer;
an insulator layer on the first fin structures and the second fin structures, wherein the insulator layer comprises a first portion on the first fin structures and a second portion on the second fin structures, and wherein the first portion of the insulator layer is thicker than the second portion of the insulator layer;
a gate conductor intersecting the first fin structures and the second fin structures, wherein at least the insulator layer separates the gate conductor from the first fin structures and the second fin structures; and
source and drain structures on the first fin structures and the second fin structures laterally adjacent the gate conductor,
wherein the first fin structures have sidewalls that include a step at a location where the first fin structures intersect the surface of the isolation layer,
wherein the second fin structures have sidewalls that do not include the step, and
wherein the step is approximately parallel to the surface of the isolation layer.
9. The integrated circuit device in claim 8 , wherein a portion of the first fin structures extending from the isolation layer are thinner relative to a portion of the second fin structures extending from the isolation layer.
10. The integrated circuit device in claim 8 , where a first distance between adjacent ones of the first fin structures is greater than a second distance between adjacent ones of the second fin structures.
11. The integrated circuit device in claim 8 ,
wherein the first portion of the insulator layer comprises at least two layers of different insulating materials, and
wherein the second portion of the insulator layer comprises relatively less layers of insulating materials relative to the first portion of the insulator layer.
12. The integrated circuit device in claim 11 , wherein the at least two layers of different insulating materials comprise an oxide layer and a high-k insulator layer, and wherein the relatively less layers comprises only the high-k insulator layer.
13. The integrated circuit device in claim 8 , further comprising a work function metal layer between the gate conductor and the insulator layer.