Integrated circuit fin structure
An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.
1. An integrated circuit (IC) device comprising:
first through third rows of fin field-effect transistors (FinFETs), wherein
the second row is between and adjacent to each of the first and third rows,
the FinFETs of the first row are one of an n-type or p-type,
the FinFETs of the second and third rows are the other of the n-type or p-type,
the FinFETs of the first and third rows comprise a first total number of fins, and
the FinFETs of the second row comprise a second total number of fins one greater or fewer than the first total number of fins.
2. The IC device of claim 1 , wherein some or all of the FinFETs of the first and second rows are configured as one or more logic gates.
3. The IC device of claim 1 , further comprising:
a fourth row of the other of the n-type or p-type FinFETs adjacent to the third row, aligned with the second row, separated from the second row by a gap, and comprising the second total number of fins being one fewer than the first total number of fins; and
a fifth row of the one of the n-type or p-type FinFETs adjacent to the fourth row, aligned with the first row, separated from the first row by the gap, and comprising the second total number of fins.
4. The IC device of claim 3 , wherein the fins of the FinFETs of the fifth row of FinFETs are aligned with a subset of the fins of the FinFETs of the first row of FinFETs farthest from the second row of FinFETs.
5. The IC device of claim 3 , wherein the gap between the first and second rows and the fourth and fifth rows spans a distance ranging from 20 nanometers (nm) to 150 nm.
6. The IC device of claim 1 , further comprising a fourth row of FinFETs adjacent to the third row, wherein
the third row is between the second and fourth rows, and
the FinFETs of the fourth row are the one of the n-type or p-type and comprise the second total number of fins.
7. The IC device of claim 1 , wherein the fins of the FinFETs of the first row of FinFETs are separated from corresponding fins of the FinFETs of the third row of FinFETs by a distance ranging from 100 nanometers (nm) to 400 nm.
8. An integrated circuit (IC) device comprising:
first through third rows of fin field-effect transistors (FinFETs), wherein
the second row is between and adjacent to each of the first and third rows,
the FinFETs of the first row are one of an n-type or p-type,
the FinFETs of the second and third rows are the other of the n-type or p-type,
the FinFETs of the first and third rows comprise a first total number of fins in respective first and third active areas having a first height,
the FinFETs of the second row comprise a second total number of fins in a second active area having a second height less than the first height, and
the second total number of fins is one fewer than the first total number of fins.
9. The IC device of claim 8 , further comprising:
a fourth row of the other of the n-type or p-type FinFETs adjacent to the third row, aligned with the second row, separated from the second row by a gap, and comprising the second total number of fins in a fourth active area having the second height; and
a fifth row of the one of the n-type or p-type FinFETs adjacent to the fourth row, aligned with the first row, separated from the first row by the gap, and comprising the second total number of fins in a fifth active area having the second height.
10. The IC device of claim 9 , wherein a distance between the fourth and fifth active areas is greater than a distance between the first and second active areas.
11. The IC device of claim 10 , further comprising:
a sixth row of the one of the n-type or p-type FinFETs adjacent to the first and fifth rows and comprising fins in a sixth active area,
wherein a distance between the first and sixth active areas is equal to a distance between the fifth and sixth active areas.
12. The IC device of claim 8 , further comprising a fourth row of FinFETs adjacent to the third row, wherein
the third row is between the second and fourth rows, and
the FinFETs of the fourth row are the one of the n-type or p-type and comprise the second total number of fins in a fourth active area having the second height.
13. The IC device of claim 12 , further comprising fifth through eighth rows of FinFETs, wherein
the FinFETs of the fifth row are adjacent to the FinFETs of the fourth row, are the one of the n-type or p-type, and comprise the first total number of fins in a fifth active area having the first height,
the FinFETs of the sixth row are adjacent to the FinFETs of the fifth row, are the other of the n-type or p-type, and comprise the second total number of fins in a sixth active area having the second height,
the FinFETs of the seventh row are adjacent to the FinFETs of the sixth row, are the other of the n-type or p-type, and comprise the first total number of fins in a seventh active area having the first height, and
the FinFETs of the eighth row are adjacent to the FinFETs of the seventh row, are the one of the n-type or p-type, and comprise the second total number of fins in an eighth active area having the second height.
14. The IC device of claim 8 , wherein
the first height has a value ranging from 45 nanometers (nm) to 85 nm, and
the second height has a value ranging from 35 nm to 50 nm.
15. An integrated circuit (IC) device comprising:
first through third rows of fin field-effect transistors (FinFETs), wherein
the second row is between and adjacent to each of the first and third rows,
the FinFETs of the first row are a first type of an n-type or p-type,
the FinFETs of the second and third rows are a second type of the n-type or p-type,
the FinFETs of the first and third rows comprise a total of three fins, and
the FinFETs of the second row comprise a total of two fins.
16. The IC device of claim 15 , wherein some or all of the FinFETs of the first and second rows are configured as one or more of a NOR gate, a NAND gate, an AOI gate, or an OAI gate.
17. The IC device of claim 15 , further comprising:
a fourth row of the second type of FinFETs adjacent to the third row, aligned with and separated from the second row, and comprising a total of two fins; and
a fifth row of the first type of FinFETs adjacent to the fourth row, aligned with and separated from the first row, and comprising a total of two fins.
18. The IC device of claim 17 , wherein the two fins of the FinFETs of the fifth row are aligned with the two of the three fins of the FinFETs of the first row farthest from the FinFETs of the second row.
19. The IC device of claim 15 , further comprising a fourth row of the first type of FinFETs adjacent to the third row, wherein
the third row is between the second and fourth rows, and
the FinFETs of the fourth row comprise a total of two fins.
20. The IC device of claim 19 , further comprising fifth through eighth rows of FinFETs, wherein
the FinFETs of the fifth row are adjacent to the FinFETs of the fourth row, are the first type, and comprise a total of three fins,
the FinFETs of the sixth row are adjacent to the FinFETs of the fifth row, are the second type, and comprise a total of two fins,
the FinFETs of the seventh row are adjacent to the FinFETs of the sixth row, are the second type, and comprise a total of three fins, and
the FinFETs of the eighth row are adjacent to the FinFETs of the seventh row, are the first type, and comprise a total of two fins.