Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same
A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a drain-select-level electrically conductive layer located over the alternating stack. Memory stack structures extend through the alternating stack and the drain-select-level electrically conductive layer. Dielectric divider structures including a respective pair of straight sidewalls and drain-select-level isolation structures including a respective pair of sidewalls that include a respective set of concave vertical sidewall segments divide the drain-select-level electrically conductive layer into multiple strips. The drain-select-level electrically conductive layer and the drain-select-level isolation structures are formed by replacement of a drain-select-level sacrificial material layer with a conductive material and by replacement of drain-select-level sacrificial line structures with dielectric material portions.
1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate;
a plurality of multi-level drain side select gate electrodes, each comprising a respective vertical connection portion and a respective set of drain-side-select-level electrically conductive layers that are vertically spaced apart among one another and are located over the alternating stack, wherein the respective vertical connection portion contacts, and is electrically connected, to the respective set of drain-side-select-level electrically conductive layers;
memory stack structures comprising a respective vertical semiconductor channel and a respective memory film, wherein each memory film has a respective sidewall that extends through the alternating stack and each level of the plurality of multi-level drain side select gate electrodes; and
a first drain-side-select-level isolation structure overlying the alternating stack, laterally extending along a first horizontal direction and located between a neighboring pair of the plurality of multi-level drain side select gate electrodes, and including a pair of sidewalls that include a respective set of concave vertical sidewall segments,
wherein:
at least one multi-level drain side select gate electrode of the plurality of multi-level drain side select gate electrodes contacts a sidewall of the first drain-side-select-level isolation structure; the multi-level drain side select gate electrode comprises a metallic barrier layer and a metallic fill material portion;
an upper portion of some of the memory stack structures is surrounded by a respective one of the plurality of multi-level drain side select gate electrodes;
each vertical connection portion of the multi-level drain side select gate electrodes comprises a sidewall including concave vertical sidewall segments located between a pair of the memory stack structures;
the three-dimensional memory device comprises a dielectric divider structure including a pair of straight sidewalls that laterally extend along the first horizontal direction and vertically extending through the alternating stack;
the dielectric divider structure is laterally spaced from the first drain-side-select-level isolation structures; and
the three-dimensional memory device comprises a vertical metallic spacer contacting a sidewall of the dielectric divider structure and a second drain-side-select-level isolation structure laterally spaced from the first drain-side-select-level isolation structure.
2. The three-dimensional memory device of claim 1 , wherein the vertical metallic spacer comprises:
an additional metallic barrier layer having a same composition and a same thickness as the metallic barrier layer of the plurality of multi-level drain side select gate electrodes; and
an additional metallic fill material portion having a same composition as the metallic fill material portion of the plurality of multi-level drain side select gate electrodes.
3. The three-dimensional memory device of claim 1 , wherein the second drain-side-select-level isolation structure overlies the alternating stack, laterally extends along a first horizontal direction, and includes a sidewall including a set of concave vertical sidewall segments on one side and a vertical sidewall that laterally extends along the first horizontal direction and contacts the vertical metallic spacer on another side.