Integration of III-V devices on Si wafers
An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.
1. An electronic device, comprising:
a mesa structure having a top surface and a sidewall on a substrate, wherein the mesa structure is aligned along a {0001} crystal orientation;
a first insulating layer on the sidewall of the mesa structure;
a III-V material layer on the top surface of the mesa structure, wherein the III-V material layer has a lateral epitaxial overgrowth portion on the first insulating layer.
2. The electronic device of claim 1 , further comprising a nucleation layer on the top portion of the mesa structure.
3. The electronic device of claim 1 , further comprising a device layer on the lateral epitaxial overgrowth portion.
4. The electronic device of claim 1 , wherein the III-V material layer includes GaN and the mesa structure includes silicon.
5. The electronic device of claim 1 , wherein the first insulating layer includes silicon oxide, silicon nitride, or a combination thereof.
6. The electronic device of claim 1 , wherein the mesa structure is within a trench in a second insulating layer on the substrate.
7. The electronic device of claim 1 , wherein the mesa structure has a square shape; rectangular shape, or a polygon shape.
8. The electronic device of claim 1 , wherein the lateral epitaxial overgrowth portion layer is in direct contact with the first insulating layer.
9. The electronic device of claim 1 , wherein a bottom surface of the laterally extended III-V material layer is not in direct contact with the insulating layer.
10. The electronic device of claim 1 , wherein the size of at least one of the mesa structures is from 2 microns to 10 microns.
11. A system comprising:
a chip including an electronic device comprising a mesa structure having a top surface and a sidewall on a substrate, wherein the mesa structure is aligned along a {0001} crystal orientation;
a first insulating layer on the sidewall of the mesa structure;
a III-V material layer on the top surface of the mesa structure, wherein the III-V material layer has a lateral epitaxial overgrowth portion on the first insulating layer.
12. The system of claim 11 , further comprising a nucleation layer on the top portion of the mesa structure.
13. A method to manufacture an electronic device comprising:
forming a mesa structure comprising a top surface and a sidewall on a substrate;
depositing a first insulating layer on the sidewall of the mesa structure;
depositing a III-V material layer on the top surface of the mesa structure; and
laterally growing the III-V material layer from the top surface over the first insulating layer, wherein forming the mesa structure comprises:
depositing a mask layer in a trench in a second insulating layer on the substrate;
patterning the mask layer; and
etching the substrate through the patterned mask layer.
14. The method of claim 13 , further comprising depositing a nucleation layer on the top surface of the mesa structure.
15. The method of claim 13 , further comprising depositing a device layer on the laterally grown III-V material layer.
16. The method of claim 13 , wherein the laterally grown III-V material layer is in a direct contact with the first insulating layer.
17. The method of claim 13 , wherein the III-V material layer is separated from the first insulating layer by a space.
18. The method of claim 13 , further comprising depositing a second insulating layer on the substrate; patterning the second insulating layer; etching the substrate through the patterned second insulating layer to form the trench.