Semiconductor device and method of manufacturing the same
Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
1. A semiconductor device comprising:
a semiconductor substrate having a first main surface and a second main surface opposing to the first main surface;
a trench formed in the first main surface;
a gate insulating film formed on an inner surface of the trench;
a gate electrode formed on the gate insulating film to fill in the trench;
a channel region formed in the first main surface at a side of the trench;
a source region formed in the channel region at the side of the trench;
a drift layer formed in the semiconductor substrate under the channel region;
a drain region formed in the second main surface and under the drift layer;
a drain electrode formed on the second main surface and in contact with the drain region, the gate electrode, the channel region, the source region and the drain region serving as a vertical type MOSFET; and
a capacitor element formed on the first main surface to stack over the vertical type MOSFET, the capacitor element including a first electrode electrically coupled to the source region, a second electrode electrically coupled to the drain region and an insulating film formed between the first and second electrodes,
wherein the vertical type MOSFET and the capacitor element are disposed in an active region of the semiconductor substrate in a plan view,
wherein the second electrode of the capacitor element extends from the active region to a peripheral region of the semiconductor substrate which is outside the active region in the plan view, and
wherein the second electrode of the capacitor element is electrically coupled to the drain region at the peripheral region of the semiconductor substrate in the plan view.
2. The semiconductor device according to claim 1 ,
wherein the channel region is formed of a P-type semiconductor layer, and
wherein the source region, the drain region and the drift layer are formed of an N-type semiconductor layer, respectively.
3. The semiconductor device according to claim 2 ,
wherein the gate electrode is formed of a polycrystalline silicon film.
4. The semiconductor device according to claim 3 ,
wherein each of the first electrode and the second electrode of the capacitor element is formed of an aluminum film, respectively, and
wherein the aluminum film of the first electrode is in a different layer from the aluminum film of the second electrode.
5. The semiconductor device according to claim 4 ,
wherein the second electrode of the capacitor element is formed to be stacked over the first electrode of the capacitor element in a thickness direction of the semiconductor substrate.