Inspection method, inspection system, and method of manufacturing semiconductor package using the same

1. A method of manufacturing a semiconductor package, the method comprising:

forming a first pattern group on a substrate;

measuring a first image of the first pattern group to generate first layout data based on the first image;

forming an interlayer layer on the first pattern group;

forming a second pattern group on the interlayer layer;

measuring a second image of the second pattern group to generate second layout data based on the second image subsequent to forming the interlayer layer;

measuring a third image including the first image and the second image to generate third layout data based on the third image; and

detecting a defect pattern based on the first layout data, the second layout data, and the third layout data, the defect pattern being at a height from the substrate between the first pattern group and the second pattern group.

2. The method of claim 1 , wherein

the defect pattern is in the interlayer layer between the first pattern group and the second pattern group, and

the third image includes an image of the defect pattern.

3. The method of claim 2 , wherein the detecting of the defect pattern comprises:

comparing the third layout data with the first layout data and the second layout data; and

selecting a portion of the third layout data as an information of the defect pattern such that the portion of the third layout data does not coincide with the first layout data and the second layout data.

4. The method of claim 1 , wherein

the first image and the second image are obtained using a first optical system,

the third image is obtained using a second optical system, and

the second optical system has a depth of focus greater than that of the first optical system.

5. The method of claim 1 , wherein

the first image and the second image are obtained using a first optical system including a first light source, and

the third image is obtained using a second optical system including a second light source different from the first light source.

6. The method of claim 5 , wherein

a first light of the first light source is incident in a direction inclined to a top surface of the substrate, and

a second light of the second light source is incident in a direction vertical to the top surface of the substrate.

7. The method of claim 5 , wherein

the first optical system is a dark-field illumination system, and

the second optical system is a bright-field illumination system.

8. A method of manufacturing a semiconductor package, the method comprising:

forming a first pattern group on a substrate;

measuring a first image of the first pattern group to generate first layout data based on the first image, the first image obtained using a first light source;

forming an interlayer layer on the first pattern group;

forming a second pattern group on the interlayer layer;

measuring a second image of the second pattern group to generate second layout data based on the second image subsequent to forming the interlayer layer, the second image obtained using the first light source;

measuring a third image including the first image and the second image to generate third layout data based on the third image, the third image obtained using a second light source different from the first light source; and

detecting a defect pattern based on the first layout data, the second layout data, and the third layout data, the defect pattern being at a height from the substrate between the first pattern group and the second pattern group.

9. The method of claim 8 , wherein the detecting of the defect pattern comprises:

comparing the third layout data with the first layout data and the second layout data; and

selecting a portion of the third layout data as an information of the defect pattern such that the portion of the third layout data does not coincide with the first layout data and the second layout data.

10. The method of claim 8 , wherein the substrate comprises:

a support substrate including a plurality of cavities penetrating the support substrate;

semiconductor chips in the plurality of cavities; and

a mold layer on a first surface of the support substrate to cover the semiconductor chips, the mold layer extending into the cavities such that the mold layer is between the support substrate and the semiconductor chips, wherein

the first pattern group, the second pattern group, and the defect pattern are on a second surface of the support substrate, the second surface being opposite the first surface.

11. The method of claim 10 , wherein:

the first and second pattern groups include interconnection line patterns, the interconnection line patterns configured to electrically connect the semiconductor chips to external terminals, and

the defect pattern is in a transparent or translucent insulating layer between the first pattern group and the second pattern group.

12. The method of claim 8 , wherein a first light of the first light source is incident in a direction inclined to a top surface of the substrate.

13. The method of claim 8 , wherein a second light of the second light source is incident in a direction vertical to a top surface of the substrate.

14. The method of claim 8 , wherein the first image and the second image are obtained using a first optical system including the first light source,

the third image is obtained using a second optical system including the second light source, and

the second optical system has a depth of focus greater than that of the first optical system.

15. The method of claim 14 , wherein the first optical system is a dark-field illumination system, and the second optical system is a bright-field illumination system.

16. The method of claim 8 , wherein a first light of the first light source is incident in a direction inclined to a top surface of the substrate, and a second light of the second light source is incident in a direction vertical to a top surface of the substrate.

17. A method of manufacturing a semiconductor package, the method comprising:

forming a first pattern group on a substrate;

measuring a first image of the first pattern group to generate first layout data based on the first image, the first image obtained using a first light source configuring a dark-field illumination system;

forming an interlayer layer on the first pattern group;

forming a second pattern group on the interlayer layer;

measuring a second image of the second pattern group to generate second layout data based on the second image subsequent to forming the interlayer layer, the second image obtained using the first light source;

measuring a third image including the first image and the second image to generate third layout data based on the third image, the third image obtained using a second light source configuring a bright-field illumination system; and

detecting a defect pattern based on the first layout data, the second layout data, and the third layout data, the defect pattern being at a height from the substrate between the first pattern group and the second pattern group.

18. The method of claim 17 , wherein the defect pattern is in the interlayer layer between the first pattern group and the second pattern group.

19. The method of claim 18 , wherein the third image includes an image of the defect pattern, and wherein the detecting of the defect pattern comprises:

comparing the third layout data with the first layout data and the second layout data; and

selecting a portion of the third layout data as an information of the defect pattern such that the portion of the third layout data does not coincide with the first layout data and the second layout data.

20. The method of claim 17 , wherein the substrate comprises:

a support substrate including a plurality of cavities penetrating the support substrate;

semiconductor chips in the plurality of cavities; and

a mold layer on a first surface of the support substrate to cover the semiconductor chips, the mold layer extending into the cavities such that the mold layer is between the support substrate and the semiconductor chips, wherein

the first pattern group, the second pattern group, and the defect pattern are on a second surface of the support substrate, the second surface being opposite the first surface,

the first and second pattern groups include interconnection line patterns, the interconnection line patterns configured to electrically connect the semiconductor chips to external terminals, and

the defect pattern is in a transparent or translucent insulating layer between the first pattern group and the second pattern group.