Semiconductor memory device
A semiconductor memory device includes free magnetic pattern on a substrate, a reference magnetic pattern on the free magnetic pattern, the reference magnetic pattern including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns, a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, a polarization enhancement magnetic pattern between the tunnel barrier pattern and the first pinned pattern, and an intervening pattern between the polarization enhancement magnetic pattern and the first pinned pattern, wherein the first pinned pattern includes first ferromagnetic patterns and anti-ferromagnetic exchange coupling patterns which are alternately stacked.
1. A semiconductor device comprising:
a substrate;
a reference magnetic pattern disposed on the substrate, and including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern;
an intervening pattern disposed on the reference magnetic pattern;
a polarization enhancement magnetic pattern disposed on the intervening pattern;
a tunnel barrier pattern disposed on the polarization enhancement magnetic pattern; and
a free magnetic pattern disposed on the tunnel barrier pattern,
wherein the exchange coupling pattern is disposed on the second pinned pattern,
the first pinned pattern is disposed on the exchange coupling pattern,
the first pinned pattern includes first ferromagnetic patterns and first non-magnetic patterns that are alternately stacked,
the first ferromagnetic patterns includes cobalt (Co),
the first non-magnetic patterns includes iridium (Ir), and
the second pinned pattern includes cobalt-platinum (CoPt) and/or CoPt alloy.
2. The semiconductor device of claim 1 , wherein each of the first non-magnetic patterns includes a non-magnetic material that couples adjacent first ferromagnetic patterns to have magnetic moments of the adjacent first ferromagnetic patterns anti-parallel to each other.
3. The semiconductor device of claim 1 , wherein the second pinned pattern includes a first element that is the same ferromagnetic material as the first ferromagnetic patterns, and a second element that is a different non-magnetic material from the first non-magnetic patterns.
4. The semiconductor device of claim 1 , wherein the first pinned pattern has a different crystal structure from the polarization enhancement magnetic pattern.
5. The semiconductor device of claim 1 , wherein the polarization enhancement magnetic pattern has the same crystal structure as the free magnetic pattern.
6. The semiconductor device of claim 1 , wherein the intervening pattern contacts first one of the first ferromagnetic patterns, and
the exchange coupling pattern contacts second one of the first ferromagnetic patterns.
7. The semiconductor device of claim 1 , further comprising an interlayer insulating layer disposed between the substrate and the reference magnetic pattern.
8. The semiconductor device of claim 7 , further comprising a contact plug penetrating the interlayer insulating layer.
9. The semiconductor device of claim 1 , wherein the tunnel barrier pattern includes a plurality of layers.
10. A semiconductor device comprising:
a substrate;
a reference magnetic pattern disposed on the substrate, and including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern;
an intervening pattern disposed on the reference magnetic pattern;
a polarization enhancement magnetic pattern disposed on the intervening pattern;
a tunnel barrier pattern disposed on the polarization enhancement magnetic pattern; and
a free magnetic pattern disposed on the tunnel barrier pattern,
wherein the exchange coupling pattern is disposed on the second pinned pattern,
the first pinned pattern is disposed on the exchange coupling pattern,
the first pinned pattern includes first ferromagnetic patterns and first non-magnetic patterns that are alternately stacked,
each of the first non-magnetic patterns includes a non-magnetic material having an anti-ferromagnetic coupling property, and
the second pinned pattern includes CoPt or CoPt alloy.
11. The semiconductor device of claim 10 , wherein the first ferromagnetic patterns includes cobalt (Co), and
the first non-magnetic patterns includes iridium (Ir).
12. The semiconductor device of claim 10 , wherein the non-magnetic material included in each of the first non-magnetic patterns couples adjacent first ferromagnetic patterns to have magnetic moments of the adjacent first ferromagnetic patterns anti-parallel to each other.
13. The semiconductor device of claim 10 , wherein the number of the first ferromagnetic patterns included in the first pinned pattern is an odd number, and
the number of the first non-magnetic patterns included in the first pinned pattern is an even number.
14. The semiconductor device of claim 10 , wherein the exchange coupling pattern couples the first pinned pattern and the second pinned pattern to each other.
15. The semiconductor device of claim 10 , wherein the exchange coupling pattern includes ruthenium (Ru), iridium (Ir), chromium (Cr) or rhodium (Rh).
16. A semiconductor device comprising:
a substrate;
a reference magnetic pattern disposed on the substrate, and including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern;
an intervening pattern disposed on the reference magnetic pattern;
a polarization enhancement magnetic pattern disposed on the intervening pattern;
a tunnel barrier pattern disposed on the polarization enhancement magnetic pattern; and
a free magnetic pattern disposed on the tunnel barrier pattern,
wherein the exchange coupling pattern is disposed on the second pinned pattern,
the first pinned pattern is disposed on the exchange coupling pattern,
the first pinned pattern includes first ferromagnetic patterns and first non-magnetic patterns that are alternately stacked,
the first ferromagnetic patterns includes cobalt (Co),
the first non-magnetic patterns includes iridium (Ir), and
the second pinned pattern includes a first element that is the same ferromagnetic material as the first ferromagnetic patterns, and a second element that is a different non-magnetic material from the first non-magnetic patterns.
17. The semiconductor device of claim 16 , wherein the second pinned pattern includes CoPt or CoPt alloy.
18. The semiconductor device of claim 16 , wherein each of the first non-magnetic patterns includes a non-magnetic material that couples adjacent first ferromagnetic patterns to have magnetic moments of the adjacent first ferromagnetic patterns anti-parallel to each other.
19. The semiconductor device of claim 16 , wherein the intervening pattern contacts first one of the first ferromagnetic patterns, and
the exchange coupling pattern contacts second one of the first ferromagnetic patterns.
20. The semiconductor device of claim 16 , wherein the polarization enhancement magnetic pattern includes cobalt (Co), iron (Fe) or nickel (Ni).