IP Library › Granted Patent US 10,490,516
Granted Patent B2
US 10,490,516 · App. 15/870,708 · Granted Nov 26, 2019

Packaged integrated circuit device with cantilever structure

Inventors: John G. Meyers (Sacramento, CA); Bilal Khalaf (Folsom, CA); Sireesha Gogineni (Folsom, CA); Brian J. Long (Folsom, CA)
Assignee: Intel Corporation
H01L23/585H01L21/52H01L22/34H01L23/13H01L23/3121H01L25/0657H01L25/16H01L25/50H01L22/32H01L23/49816H01L24/16H01L24/32H01L24/48H01L24/73H01L2223/6677H01L2224/16227H01L2224/16235H01L2224/32145H01L2224/32225H01L2224/48091H01L2224/48145H01L2224/48147H01L2224/48227H01L2224/73265H01L2225/0651H01L2225/06506H01L2225/06555H01L2225/06562H01L2225/06572H01L2225/06593H01L2225/06596H01L2924/00014H01L2924/1433H01L2924/1436H01L2924/1531H01L2924/15162H01L2924/15192H01L2924/15311H01L2924/15331H01L2924/15333H01L2924/1815H01L2924/19041H01L2924/19042H01L2924/19043H01L2924/19105H01L2924/19106
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Quick Facts
Patent No.
US 10,490,516
App. No.
15/870,708
Granted
Nov 26, 2019
Kind
B2
Abstract

Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.

Claims (10)

1. A system comprising a packaged device including:

a first package including a package material and one or more integrated circuit (IC) dies disposed in the package material, wherein the first package includes a first side, a second side, and a sidewall structure extending between a first edge of the first side and a second edge of the second side;

a first substrate disposed to the first side, wherein one of the first side and the second side is offset from a line extending from a first cantilever portion of the first substrate in a direction perpendicular to the first side;

circuitry disposed on the first substrate, wherein the one or more IC dies is coupled to the circuitry via the first substrate, the circuitry including a circuit structure disposed on the first cantilever portion; and

a second substrate disposed to the second side, wherein the one or more IC are dies coupled via the second substrate to a hardware interface disposed in or on a surface of the second substrate; and

a display device coupled to the packaged device, the display device to display an image based on signals exchanged with the one or more IC dies.

2. The system of claim 1 , wherein only one of the first side and the second side is offset from the line.

3. The system of claim 1 , wherein the circuit structure is an interface contact.

4. The system of claim 1 , wherein the circuit structure is disposed on a side of the first cantilever portion that faces toward the second substrate.

5. The system of claim 1 , wherein the first substrate forms a second cantilever portion that extends past an edge of the first package.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072905/0252 →
Continuity (2)
Division 14866576 · Sep 25, 2015
Related Publication 20180138133A1 · May 17, 2018