Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors
Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.
1. A semiconductor device, comprising:
a fin on a region of a substrate; and
an embedded bottom contact formed on a recessed portion of the region along three sides of the fin, a topmost surface of the embedded bottom contact below a bottommost surface of the fin.
2. The semiconductor device of claim 1 , wherein the embedded bottom contact comprises a thickness of about 7 to about 12 nm.
3. The semiconductor device of claim 1 , wherein the region of the substrate comprises a dopant.
4. The semiconductor device of claim 1 further comprising a gate over a channel region of the fin.
5. The semiconductor device of claim 4 further comprising a bottom spacer between the region of the substrate and the gate.
6. The semiconductor device of claim 5 further comprising a top spacer over the gate and the bottom spacer.
7. The semiconductor device of claim 1 further comprising a conductive contact on a surface of the fin.
8. The semiconductor device of claim 1 further comprising a conductive contact on a surface of the embedded contact.
9. The semiconductor device of claim 1 , wherein the embedded contact comprises a metal.
10. The semiconductor device of claim 1 , wherein the embedded contact comprises titanium.
11. A semiconductor device, comprising:
a fin on a region of a substrate;
a gate formed over a channel region of the fin;
a conductive rail on a recessed portion of the region of the substrate, a topmost surface of the conductive rail below a bottommost surface of the fin;
a first conductive contact on a surface of the conductive rail; and
a second conductive contact on a surface of the fin.
12. The semiconductor device of claim 11 , wherein the region of the substrate comprises a dopant.
13. The semiconductor device of claim 12 , wherein conductive rail comprises a metal.
14. The semiconductor device of claim 12 , wherein the conductive rail has a higher conductivity than the region of the substrate comprising the dopant.
15. The semiconductor device of claim 11 further comprising a bottom spacer between the region of the substrate and the gate.
16. The semiconductor device of claim 15 further comprising a top spacer over the gate and the bottom spacer.
17. The semiconductor device of claim 11 , wherein the conductive rail wraps around three sides of the fin.
18. The semiconductor device of claim 11 , wherein the conductive rail comprises a thickness of about 7 to about 12 nm.
19. The semiconductor device of claim 11 , wherein the conductive rail comprises titanium.
20. The semiconductor device of claim 11 , wherein the region of the substrate comprises a dopant and forms a source/drain region.