Memory device and fabrication thereof

1. A memory device, comprising:

a bottom electrode over a metallization layer embedded in an inter-metal dielectric layer, the bottom electrode having a bottom surface, a top surface and a sidewall that extends at an obtuse angle relative to the top surface and is curved from the bottom surface of the bottom electrode to the top surface of the bottom electrode;

a resistance switching layer over the bottom electrode; and

a top electrode over the resistance switching layer.

2. The memory device of claim 1 , wherein the sidewall of the bottom electrode is convex.

3. The memory device of claim 1 , further comprising:

a polish stop layer surrounding the bottom electrode, the polish stop layer having a top surface and a sidewall that extends at an acute angle relative to the top surface of the polish stop layer.

4. The memory device of claim 3 , wherein the sidewall of the polish stop layer is in contact with the sidewall of the bottom electrode.

5. The memory device of claim 3 , wherein the sidewall of the polish stop layer is curved.

6. The memory device of claim 3 , wherein the sidewall of the polish stop layer is concave.

7. The memory device of claim 3 , wherein the sidewall of the polish stop layer has a curvature substantially the same as a curvature of the sidewall of the bottom electrode.

8. The memory device of claim 3 , wherein the sidewall of the polish stop layer has a slope substantially the same as a slope of the sidewall of the bottom electrode.

9. The memory device of claim 1 , wherein the resistance switching layer has a sidewall with a different shape than the sidewall of the bottom electrode.

10. The memory device of claim 1 , wherein the top electrode has a sidewall with a different shape than the sidewall of the bottom electrode.

11. A memory device, comprising:

a bottom electrode over a metal structure surrounded by a dielectric layer;

a top electrode above the bottom electrode; and

a resistance switching layer between the bottom electrode and the top electrode, wherein the bottom electrode comprises a top portion tapering towards and in contact with the resistance switching layer and a distance between opposite edges of a top surface of the bottom electrode is less than a distance between opposite edges of a bottom surface of the resistance switching layer.

12. The memory device of claim 11 , wherein the top portion of the bottom electrode has a convex sidewall in contact with the dielectric layer.

13. The memory device of claim 11 , wherein the top portion of the bottom electrode has a sloped sidewall in contact with the dielectric layer.

14. The memory device of claim 11 , wherein the bottom electrode further comprises a bottom portion between the top portion and the metal structure, and the bottom portion tapers away from the top portion.

15. The memory device of claim 14 , wherein the bottom portion has a convex sidewall.

16. The memory device of claim 11 , wherein the bottom electrode further comprises a trapezoidal bottom portion between the top portion and the metal structure.

17. A memory device, comprising:

a bottom electrode over a metal structure surrounded by a first dielectric layer;

a second dielectric layer surrounding the bottom electrode and having a top surface substantially level with a top surface of the bottom electrode;

a top electrode above the bottom electrode; and

a resistance switching layer between the bottom electrode and the top electrode, wherein the bottom electrode has a middle portion and an upper portion between the middle portion and the resistance switching layer, and a width of the upper portion is less than a width of the middle portion of the bottom electrode when viewed in cross-section.

18. The memory device of claim 17 , wherein a sidewall of the upper portion of the bottom electrode extends at an acute angle relative to the top surface of the second dielectric layer.

19. The memory device of claim 11 , wherein an area of the top surface of the bottom electrode is less than an area of the bottom surface of the resistance switching layer.

20. The memory device of claim 17 , wherein an entirety of the resistance switching layer is above the top surface of the second dielectric layer.