Resistive random access memory structure and manufacturing method thereof
The invention provides a resistive random access memory (RRAM) structure, which comprises a lower electrode located on a substrate, a resistance switching layer located on the lower electrode, and an upper electrode located on the resistance switching layer, the resistive random access memory structure has a flat top surface and two inclined sidewalls as viewed from a sectional view, and the maximum width of the resistance switching layer is greater than the maximum width of the upper electrode.
1 . A resistive random access memory (RRAM) structure, comprising:
a lower electrode located on a substrate;
a resistance switching layer located on the lower electrode; and
an upper electrode located on the resistance switching layer, wherein the resistance random access memory structure has a flat top surface and two inclined sidewalls when viewed from a cross section, and a maximum width of the resistance switching layer is greater than a maximum width of the upper electrode, wherein when viewed from a cross section, the resistance switching layer comprises a convex part, and the upper electrode has a flat top surface and two inclined sidewalls, and covers the convex part of the resistance switching layer.
2 . The resistive random access memory structure according to claim 1 , wherein the lower electrode has a triangular or trapezoidal cross-sectional structure.
3 . The resistive random access memory structure according to claim 1 , wherein the resistance switching layer comprises a multi-layer structure comprising a first material layer and a second material layer stacked from bottom to top.
4 . The resistive random access memory structure of claim 3 , wherein the first material layer comprises chromium oxide and the second material layer comprises aluminum oxide.
5 . The resistive random access memory structure according to claim 3 , wherein the first material layer directly contacts the substrate and the lower electrode.
6 . The resistive random access memory structure according to claim 3 , wherein a maximum width of the first material layer is equal to a maximum width of the second material layer.
7 . The resistive random access memory structure according to claim 3 , further comprising two spacers covering the upper electrode, wherein the spacer is made of the same material as the second material layer.
8 . The resistive random access memory structure according to claim 7 , wherein the spacer directly contacts part of the second material layer.
9 . The resistive random access memory structure according to claim 1 , wherein a maximum width of the lower electrode is smaller than a maximum width of the resistance switching layer.
10 . A method for fabricating a resistive random access memory (RRAM) structure, comprising:
forming a lower electrode on a substrate;
forming a resistance switching layer on the lower electrode; and
forming an upper electrode on the resistance switching layer, wherein the resistive random access memory structure has a flat top surface and two inclined sidewalls as viewed from a cross section, and a maximum width of the resistance switching layer is greater than a maximum width of the upper electrode, wherein when viewed from a cross section, the resistance switching layer comprises a convex part, and the upper electrode has a flat top surface and two inclined sidewalls, and covers the convex part of the resistance switching layer.
11 . The manufacturing method of the resistive random access memory structure according to claim 10 , wherein the lower electrode has a triangular or trapezoidal cross-sectional structure.
12 . The manufacturing method of the resistive random access memory structure according to claim 10 , wherein the resistance switching layer comprises a multilayer structure, and the multilayer structure comprises a first material layer and a second material layer stacked from bottom to top.
13 . The manufacturing method of the resistive random access memory structure according to claim 12 , wherein the first material layer comprises chromium oxide and the second material layer comprises aluminum oxide.
14 . The manufacturing method of the resistive random access memory structure according to claim 12 , wherein the first material layer directly contacts the substrate and the lower electrode.
15 . The manufacturing method of the resistive random access memory structure according to claim 12 , wherein a maximum width of the first material layer is equal to a maximum width of the second material layer.
16 . The manufacturing method of the resistive random access memory structure according to claim 12 , further comprising forming two spacers covering the upper electrode, wherein the spacer is made of the same material as the second material layer.
17 . The manufacturing method of the resistive random access memory structure according to claim 16 , wherein the spacer directly contacts part of the second material layer.
18 . The manufacturing method of the resistive random access memory structure according to claim 16 , wherein a maximum width of the lower electrode is smaller than a maximum width of the resistance switching layer.