Semiconductor device having memory cell structure and method of manufacturing the same
A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.
1. A semiconductor device, comprising
a lower conducting layer, formed above a substrate;
a memory cell structure, formed on the lower conducting layer, and the memory cell structure comprising:
a bottom electrode, formed on and electrically connected to the lower conducting layer;
a transitional metal oxide (TMO) layer, formed on the bottom electrode;
a TMO sidewall oxides, formed at sidewalls of the TMO layer and formed on the bottom electrode, wherein bottom surfaces of the TMO sidewall oxides are formed on and directly contact a top surface of the bottom electrode;
a top electrode, formed on the TMO layer; and
spacers, formed on the bottom electrode; and
an upper conducting layer, formed on and electrically connected to the top electrode.
2. The semiconductor device according to claim 1 , wherein the spacers are formed adjacent to the sidewalls of the TMO layer, and cover the TMO sidewall oxides and sidewalls of the top electrode.
3. The semiconductor device according to claim 2 , wherein outer walls of the TMO sidewall oxides are substantially aligned with the sidewalls of the top electrode.
4. The semiconductor device according to claim 1 , wherein bottom surfaces of the spacers are formed on and directly contact the top surface of the bottom electrode.
5. The semiconductor device according to claim 1 , wherein the spacers formed on the bottom electrode uncover sidewalls of the bottom electrode.
6. The semiconductor device according to claim 1 , wherein a width of the TMO layer is smaller than a width of the top electrode.
7. The semiconductor device according to claim 1 , wherein a width of the bottom electrode is larger than a width of the top electrode.
8. The semiconductor device according to claim 1 , wherein a width of the bottom electrode is larger than a width of the TMO layer.
9. The semiconductor device according to claim 1 , wherein the memory cell structure further comprises:
a capping electrode formed on and directly contacting the top electrode,
wherein the upper conducting layer is formed on and electrically connected to the capping electrode.
10. The semiconductor device according to claim 9 , wherein a width of the capping electrode is larger than a width of the top electrode.
11. The semiconductor device according to claim 9 , wherein the capping electrode covers top surfaces of the spacers.
12. The semiconductor device according to claim 9 , wherein the width of the capping electrode is equal to a width of the bottom electrode.
13. The semiconductor device according to claim 1 , wherein the lower conducting layer is a lower contact via connected to a lower metal line layer, and the lower contact via is filled with a conductive material.
14. The semiconductor device according to claim 13 , wherein the conductive material in the lower contact via is different from a material of the bottom electrode.
15. The semiconductor device according to claim 13 , wherein the conductive material in the lower contact via is the same as a material of the bottom electrode.
16. The semiconductor device according to claim 1 , wherein the upper conducting layer is an upper contact via connected to an upper metal line layer.
17. The semiconductor device according to claim 1 , wherein the upper conducting layer is an upper metal line layer.
18. A semiconductor device, comprising
a lower conducting layer, formed above a substrate;
a memory cell structure, formed on the lower conducting layer, and the memory cell structure comprising:
a bottom electrode, formed on and electrically connected to the lower conducting layer;
a transitional metal oxide (TMO) layer, formed on the bottom electrode;
a top electrode, formed on the TMO layer; and
spacers, formed on the bottom electrode, wherein bottom surfaces of the spacers are formed on and directly contact a top surface of the bottom electrode; and
an upper conducting layer, formed on and electrically connected to the top electrode.
19. The semiconductor device according to claim 18 , wherein the spacers formed on the bottom electrode uncover sidewalls of the bottom electrode.
20. The semiconductor device according to claim 18 , wherein the memory cell structure further comprises:
a TMO sidewall oxides, formed at sidewalls of the TMO layer, wherein the spacers are formed adjacent to the sidewalls of the TMO layer, and cover the TMO sidewall oxides and sidewalls of the top electrode.
21. The semiconductor device according to claim 18 , wherein a width of the bottom electrode is larger than a width of the TMO layer and also larger than a width of the top electrode.
22. The semiconductor device according to claim 18 , wherein the memory cell structure further comprises:
a capping electrode formed on and directly contacting the top electrode,
wherein the upper conducting layer is formed on and electrically connected to the capping electrode.
23. The semiconductor device according to claim 22 , wherein a width of the capping electrode is larger than a width of the top electrode.
24. The semiconductor device according to claim 22 , wherein the capping electrode covers top surfaces of the spacers.