Structure of flash memory cell
A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.
1. A structure of flash memory cell, comprising:
a substrate;
a floating gate, disposed on the substrate;
a low dielectric constant (low-K) spacer, disposed on a sidewall of the floating gate;
a trench isolation structure, having a base part disposed in the substrate and a protruding part above the substrate protruding from the base part; and
a tunnel oxide layer between the substrate and the floating gate,
wherein the low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure,
wherein a peripheral bottom flat surface of the floating gate directly covers on a portion of the base part of the trench isolation structure,
wherein the low-K spacer and the tunnel oxide layer are separated by a portion of the floating gate on the base part of the trench isolation structure,
wherein the low-K spacer comprises an air spacer, having a free space filled with air and a dielectric constant being close to 1,
wherein a dielectric constant of the low-K spacer is smaller than a dielectric constant of the trench isolation structure,
wherein a bottom surface of the tunnel oxide layer is lower than a bottommost surface of the low-K spacer.
2. The structure of flash memory cell in claim 1 , wherein the tunnel oxide layer is disposed on the substrate between adjacent two of the base part of the trench isolation structure.
3. The structure of flash memory cell in claim 1 , wherein the protruding part of the trench isolation structure is narrower than a top of the base part.
4. The structure of flash memory cell in claim 1 , wherein a top surface of the low-K spacer is coplanar with a top surface of the floating gate.
5. The structure of flash memory cell in claim 1 , wherein the floating gate, the low-K spacer and the protruding part of the trench isolation structure are same in thickness and height in a normal direction of the substrate.