Methods for replacing gate sidewall materials with a low-k spacer
A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.
1. A method of fabricating a semiconductor device, the method comprising:
exposing a plurality of gates comprising vertical sidewalls by stripping spacer material and liner material from the vertical sidewalls of the plurality of gates;
contiguously exposing a semiconductor substrate top surface from a first gate to a second gate by stripping the liner material from the semiconductor substrate top surface;
subsequent to exposing the plurality of gates and contiguously exposing the semiconductor substrate top surface, forming a low-k spacer layer comprising:
forming a first low-k spacer portion upon a vertical sidewall of the first gate;
forming a second low-k spacer portion upon a vertical sidewall of the second gate, and;
forming a third low-k spacer portion upon the contiguously exposed semiconductor substrate top surface between the first gate and the second gate; and
forming a fill material upon and over the third low-k spacer portion.
2. The method of claim 1 wherein the first low-k spacer portion and the second low-k spacer portion are substantially vertical.
3. The method of claim 1 wherein the third low-k spacer portion is substantially horizontal.
4. The method of claim 1 wherein the first low-k spacer portion and the second low-k spacer portion are orthogonal to the third low-k spacer portion.
5. The method of claim 1 wherein the third low-k spacer portion is formed to meet the first low-k spacer portion and the second low-k spacer portion.
6. The method of claim 1 wherein the first low-k spacer portion thickness, the second low-k spacer portion thickness, and the third low-k spacer portion thickness are the same.
7. The method of claim 1 wherein exposing a plurality of gates further comprises:
removing portions of high-k dielectric from vertical sidewalls of the plurality of gates.
8. The method of claim 7 wherein exposing a plurality of gates further comprises:
removing a plurality of spacers formed upon the high-k dielectric;
removing a liner formed upon the plurality of spacers, and;
removing fill material formed upon the liner.
9. The method of claim 1 wherein the first low-k spacer portion thickness is greater than the second low-k spacer portion thickness.
10. The method of claim 1 wherein the fill material comprises an oxide fill material.
11. The method of claim 1 wherein the fill material contacts and is between the first low-k spacer portion and the second low-k spacer portion.
12. The method of claim 1 further comprising forming a contact through the fill material and the third low-k spacer portion.
13. The method of claim 1 further comprising:
planarizing the fill material to a top surface of the first low-k spacer portion;
forming a self-aligned contact cap contacting both a top surface of the first gate and the first low-k spacer portion; and
forming an additional fill material over the self-aligned contact cap.
14. The method of claim 13 , further comprising forming a contact through the additional fill material, the fill material, and the third low-k spacer portion.
15. The method of claim 13 , wherein the self-aligned contact cap comprises silicon nitride.
16. The method of claim 1 further comprising removing a first portion of a high-k dielectric layer from the vertical sidewall of the first gate.
17. The method of claim 16 , wherein a second portion of the high-k dielectric layer comprises a gate dielectric under the first gate.
18. A method of fabricating a semiconductor device, the method comprising:
forming a semiconductor structure comprising:
a first gate structure comprising a first high-k dielectric layer, a first gate, first spacers, and a first liner;
a second gate structure comprising a second high-k dielectric layer, a second gate, second spacers, and a second liner; and
a first fill material;
exposing the first gate and the second gate by removing the fill material, removing portions of the first high-k dielectric layer and the second high-k dielectric layer, removing the first spacers and the second spacers, and removing the first liner and the second liner;
forming a low-k spacer layer on a sidewall of the first gate, a sidewall of the second gate, and a surface of a substrate between the first gate and the second gate; and
forming a second fill material on the low-k spacer layer including a horizontal portion of the low-k spacer layer that is on the surface of the substrate between the first gate and the second gate;
wherein the removing portions of the first high-k dielectric layer and the second high-k dielectric layer comprises:
removing a first portion of the first high-k dielectric layer from the sidewall of the first gate while leaving a second portion of the first high-k dielectric layer underneath the first gate; and
removing a first portion of the second high-k dielectric layer from the sidewall of the second gate while leaving a second portion of the second high-k dielectric layer underneath the second gate.
19. The method of claim 18 , further comprising forming a contact through the second fill material and the low-k spacer layer.