IP Library › Granted Patent US 12,402,367
Granted Patent B2
US 12,402,367 · App. 17/835,977 · Granted Aug 26, 2025

Semiconductor structure and manufacturing method thereof

Inventors: Kuang-Hsiu Chen (Tainan, TW); Wei-Chung Sun (Tainan, TW); Chao Nan Chen (Tainan, TW); Chun-Wei Yu (Tainan, TW); Kuan Hsuan Ku (Tainan, TW); Shao-Wei Wang (Taichung, TW)
Assignee: United Microelectronics Corp.
H10D62/021H01L21/02057H10D30/01H10D30/0223H10D30/024H10D30/797
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,402,367
App. No.
17/835,977
Granted
Aug 26, 2025
Kind
B2
Abstract

Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.

Claims (30)

1. A manufacturing method of a semiconductor structure, comprising:

forming a gate structure on a substrate;

performing a tilt implanting process to implant a group IV element into the substrate to form a doped region, wherein the doped region is located on two sides of the gate structure and partially located under the gate structure;

removing a part of the substrate on two sides of the gate structure to form a first recess;

performing a cleaning process on a surface of the first recess;

performing a wet etching process on the first recess to form a second recess; and

forming a semiconductor layer in the second recess,

wherein a forming method of the first recess comprises:

performing a first vertical etching process to remove a part of the substrate to form a first preliminary recess;

performing a lateral etching process on the first preliminary recess to remove a part of the substrate to form a second preliminary recess; and

performing a second vertical etching process on the second preliminary recess to remove a part of the substrate to form the first recess.

2. The manufacturing method of the semiconductor structure according to claim 1 , wherein the group IV element comprises carbon or germanium.

3. The manufacturing method of the semiconductor structure according to claim 1 , wherein a depth of the doped region does not exceed 200 Å.

4. The manufacturing method of the semiconductor structure according to claim 1 , wherein energy of the tilt implanting process is 1 KeV to 7 KeV.

5. The manufacturing method of the semiconductor structure according to claim 1 , wherein a middle portion of the first recess has a greater width than other portions of the first recess.

6. The manufacturing method of the semiconductor structure according to claim 1 , wherein a middle portion of the second recess has a greater width than other portions of the second recess.

7. The manufacturing method of the semiconductor structure according to claim 6 , wherein the second recess comprises an upper portion and a lower portion, the upper portion has a first inclined surface, and the lower portion has a second inclined surface, wherein an angle between a projection of a line which passes through two endpoints of the first inclined surface and a projection of a linear extension of a bottom surface of the second recess is an acute angle, an angle between a projection of a line which passes through two endpoints of the second inclined surface and the projection of the linear extension of the bottom surface of the second recess is an obtuse angle, and the first inclined surface has a convex shape or a concave shape.

8. The manufacturing method of the semiconductor structure according to claim 7 , wherein the first inclined surface has the convex shape, and the cleaning process comprises:

a first cleaning process using ammonia water and hydrogen peroxide; and

a second cleaning process using sulfuric acid and hydrogen peroxide.

9. The manufacturing method of the semiconductor structure according to claim 8 , wherein after the second cleaning process, the manufacturing method further comprises a third cleaning process using ammonia water and hydrogen peroxide.

10. The manufacturing method of the semiconductor structure according to claim 7 , wherein the first inclined surface has the concave shape, and the cleaning process comprises:

a first cleaning process using an aqueous solution containing carbon dioxide; and

a second cleaning process using sulfuric acid and hydrogen peroxide.

11. The manufacturing method of the semiconductor structure according to claim 10 , wherein after the second cleaning process, the manufacturing method further comprises a third cleaning process using ammonia water and hydrogen peroxide.

12. The manufacturing method of the semiconductor structure according to claim 7 , wherein a radius of curvature of the convex shape is 190 Å to 405 Å.

13. The manufacturing method of the semiconductor structure according to claim 7 , wherein a radius of curvature of the concave shape is 240 Å to 820 Å.

14. The manufacturing method of the semiconductor structure according to claim 1 , wherein the wet etching process comprises:

a first etching process using hydrofluoric acid; and

a second etching process using tetramethyl ammonium hydroxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2022
From: CHEN, KUANG-HSIU; SUN, WEI-CHUNG; CHEN, CHAO NAN; YU, CHUN-WEI; KU, KUAN HSUAN; WANG, SHAO-WEI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 060216/0900 →
Priority Claims (1)
TW 111117809 · May 12, 2022 · national
Continuity (1)
Related Publication 20230369460A1 · Nov 16, 2023
References Cited (16)
US 8404546B2 · Woon et al. · 2013 [cited by applicant]
US 8486587B2 · Tsai et al. · 2013 [cited by applicant]
US 9275933B2 · Kuo et al. · 2016 [cited by applicant]
US 9748139B1 · Liou et al. · 2017 [cited by applicant]
US 9761791B2 · Shiu et al. · 2017 [cited by applicant]
US 10090465B2 · Hsu et al. · 2018 [cited by applicant]
US 20050285203A1 · Fukutome · 2005 [cited by examiner]
US 20070090408A1 · Majumdar · 2007 [cited by examiner]
US 20120244674A1 · Kim · 2012 [cited by examiner]
US 20130045589A1 · Kim · 2013 [cited by examiner]
US 20160254381A1 · Kwok · 2016 [cited by examiner]
US 20220037465A1 · Lin · 2022 [cited by examiner]
CN 114141610A · 2022 [cited by examiner]
KR 102354014B1 · 2022 [cited by examiner]
TW 202139356 · 2021 [cited by applicant]
“Office Action of Taiwan Counterpart Application”, issued on May 27, 2025, p. 1-p. 5. [cited by applicant]