Vertical transistor with reduced gate length variation
Techniques for reducing gate length variation in VFET devices are provided. In one aspect, a method for forming a VFET device includes: forming a first and a second semiconductor layer as a stack on a substrate; patterning fins in the stack each of which extends completely through the second semiconductor layer and partway into the first semiconductor layer, and wherein portions of the second semiconductor layer in each of the fins include active fin channels; selectively thinning the active fin channels; forming sidewall spacers alongside the active fin channels; forming bottom source and drains at a base of the fins below the sidewall spacers; removing the sidewall spacers; forming bottom spacers on the bottom source and drains; forming gate stacks over the bottom spacers; forming top spacers on the gate stacks; and forming top source and drains on the top spacers. A VFET device is also provided.
1. A method for forming a vertical field-effect transistor (VFET) device, comprising the steps of:
forming a first semiconductor layer and a second semiconductor layer as a stack on a substrate;
patterning fins in the stack, wherein each of the fins extends completely through the second semiconductor layer and partway into the first semiconductor layer, and wherein portions of the second semiconductor layer in each of the fins comprise active fin channels;
selectively thinning the active fin channels to form a staircase structure at an interface between the active fin channels and the first semiconductor layer;
forming sidewall spacers alongside the active fin channels;
forming bottom source and drains at a base of the fins below the sidewall spacers such that tops of the bottom source and drains are flush with bottoms of the active fin channels, wherein the bottom source and drains have a contoured surface topography;
removing the sidewall spacers;
forming bottom spacers on the bottom source and drains;
forming gate stacks over the bottom spacers surrounding the active fin channels;
forming top spacers on the gate stacks; and
forming top source and drains on the top spacers.
2. The method of claim 1 , wherein the first semiconductor layer is formed having a thickness of from about 10 nm to about 50 nm and ranges therebetween, and wherein the second semiconductor layer is formed having a thickness of from about 20 nm to about 60 nm and ranges therebetween.
3. The method of claim 1 , wherein the first semiconductor layer comprises silicon germanium (SiGe) and the second semiconductor layer comprises silicon (Si).
4. The method of claim 3 , further comprising the steps of:
growing epitaxial SiGe on the substrate as the first semiconductor layer; and
growing epitaxial Si on the epitaxial SiGe as the second semiconductor layer.
5. The method of claim 1 , further comprising the steps of:
depositing a hardmask layer onto the second semiconductor layer;
patterning the hardmask layer into individual fin hardmasks; and
using the individual fin hardmasks to pattern the fins in the stack.
6. The method of claim 5 , wherein the active fin channels are selectively thinned to a final width (W FINAL ), the method further comprising the step of:
patterning the fins in the stack at an initial width (W INITIAL ), wherein W INITIAL >W FINAL .
7. The method of claim 6 , further comprising the step of:
thinning the individual fin hardmasks prior to removing the sidewall spacers.
8. The method of claim 5 , wherein the hardmask layer comprises silicon oxycarbide (SiCO).
9. The method of claim 1 , further comprising the steps of:
depositing a spacer material over the fins; and
removing the spacer material from all but alongside the active fin channels to form the sidewall spacers.
10. The method of claim 9 , wherein the spacer material comprises a dielectric spacer material selected from the group consisting of: silicon nitride (SiN), silicon oxynitride (SiON), and combinations thereof.
11. The method of claim 1 , further comprising the step of:
recessing the first semiconductor layer after the sidewall spacers are selectively formed alongside the active fin channels and prior to forming the bottom source and drains at a base of the fins.
12. The method of claim 1 , wherein the gate stacks comprise:
a gate dielectric on the active fin channels; and
a gate conductor on the gate dielectric.
13. The method of claim 1 , wherein a portion of the first semiconductor layer remains present beneath the bottom source and drains.
14. The method of claim 1 , wherein the top source and drains and the bottom source and drains each comprise a material selected from the group consisting of: phosphorous-doped Si (Si:P) and boron-doped SiGe (SiGe:B).
15. A VFET device, comprising:
a first semiconductor layer and a second semiconductor layer disposed as a stack on a substrate;
fins patterned in the stack having differing fin heights, wherein each of the fins extends completely through the second semiconductor layer and partway into the first semiconductor layer, and wherein portions of the second semiconductor layer in each of the fins comprise active fin channels having a uniform fin height;
bottom source and drains at a base of the fins, wherein tops of the bottom source and drains are flush with bottoms of the active fin channels, and wherein the bottom source and drains have a contoured surface topography;
bottom spacers on the bottom source and drains;
gate stacks over the bottom spacers surrounding the active fin channels;
top spacers on the gate stacks; and
top source and drains on the top spacers.
16. The VFET device of claim 15 , wherein a portion of the first semiconductor layer is present beneath the bottom source and drains.
17. The VFET device of claim 15 , wherein the first semiconductor layer comprises SiGe and the second semiconductor layer comprises Si.
18. The VFET device of claim 15 , wherein the gate stacks comprise:
a gate dielectric on the active fin channels; and
a gate conductor on the gate dielectric.