Semiconductor device and method
In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.
1. A method comprising:
encapsulating a light emitting diode with a photosensitive encapsulant;
forming a first opening through the photosensitive encapsulant by:
exposing the photosensitive encapsulant to light having a first pattern corresponding to the first opening; and
developing the photosensitive encapsulant; forming a second opening through the photosensitive encapsulant by:
forming a mask layer over the photosensitive encapsulant;
patterning the mask layer with a second pattern corresponding to the second opening, wherein the second opening is smaller than the first opening; and
transferring the second pattern from the mask layer to the photosensitive encapsulant; and
forming a first conductive via and a second conductive via in the first opening and the second opening, respectively.
2. The method of claim 1 , wherein transferring the second pattern from the mask layer to the photosensitive encapsulant comprises etching the photosensitive encapsulant with a plasma oxide etch.
3. The method of claim 1 , wherein the mask layer is formed of a metal-containing material.
4. The method of claim 1 , further comprising:
connecting a cathode of the light emitting diode to a first contact pad of a substrate.
5. The method of claim 4 , wherein the first conductive via is connected to an alignment mark of the substrate, and the second conductive via is connected to a second contact pad of the substrate.
6. The method of claim 5 , further comprising:
forming a third opening through the photosensitive encapsulant, the third opening exposing an anode of the light emitting diode; and
forming a conductive line in the third opening, the conductive line connecting the anode of the light emitting diode to the second conductive via.
7. The method of claim 1 , wherein the second opening is formed after the first opening.
8. A method comprising:
forming a light emitting diode by:
forming a first reflective structure over a carrier substrate, the first reflective structure comprising first doped layers of a semiconductive material;
forming an emitting semiconductor region over the first reflective structure;
forming a second reflective structure over the emitting semiconductor region, the second reflective structure comprising second doped layers of the semiconductive material; and
patterning the first reflective structure, the second reflective structure, and the emitting semiconductor region;
connecting a first terminal of the light emitting diode to an interconnect;
encapsulating the light emitting diode with a photosensitive encapsulant;
patterning first openings in the photosensitive encapsulant by exposing the photosensitive encapsulant to light and developing the photosensitive encapsulant;
patterning second openings in the photosensitive encapsulant by masking the photosensitive encapsulant and etching the photosensitive encapsulant, the second openings having a finer pitch than the first openings; and
forming conductive vias in the first openings and the second openings.
9. The method of claim 8 , wherein forming the light emitting diode further comprises:
forming a contact pad over the second reflective structure;
depositing a passivation layer over the contact pad and the second reflective structure; and
forming an underbump metallurgy extending through the passivation layer to couple the contact pad.
10. The method of claim 9 , wherein connecting the first terminal of the light emitting diode to the interconnect comprises:
forming a conductive connector electrically connecting the underbump metallurgy to the interconnect, the photosensitive encapsulant further encapsulating the conductive connector.
11. The method of claim 8 , wherein the first openings are formed above alignment marks of the interconnect and the second openings are formed above contact pads of the interconnect.
12. The method of claim 8 , wherein the second openings are formed after the first openings.
13. The method of claim 8 , further comprising:
forming a conductive line connecting a second terminal of the light emitting diode to one of the conductive vias.
14. The method of claim 8 , wherein the photosensitive encapsulant is a low temperature polyimide.
15. A method comprising:
connecting a light emitting diode to an interconnect, the light emitting diode comprising:
a first reflective structure, the first reflective structure connected to the interconnect;
a second reflective structure; and
an emitting semiconductor region disposed between the first reflective structure and the second reflective structure;
encapsulating the light emitting diode with a photosensitive encapsulant;
exposing a first portion of the photosensitive encapsulant to light;
developing the first portion of the photosensitive encapsulant to form a first opening in the photosensitive encapsulant;
patterning a hardmask over the photosensitive encapsulant by:
depositing a mask layer over the photosensitive encapsulant;
forming a photoresist over the mask layer, the photoresist having a pattern; and
transferring the pattern of the photoresist to the mask layer with a first etching process;
etching a second portion of the photosensitive encapsulant with a second etching process to form a second opening in the photosensitive encapsulant, the second etching process using the hardmask as an etching mask, the second etching process being different than the first etching process, the second opening being smaller than the first opening; and
forming a first conductive via and a second conductive via in the first opening and the second opening, respectively.
16. The method of claim 15 , wherein the second portion of the photosensitive encapsulant is etched after the first portion of the photosensitive encapsulant is developed.
17. The method of claim 15 , further comprising:
removing the hardmask before forming the first conductive via and the second conductive via.
18. The method of claim 15 , wherein the hardmask is not removed before forming the first conductive via and the second conductive via.
19. The method of claim 15 , wherein the hardmask comprises a metal.
20. The method of claim 15 , wherein the interconnect comprises an alignment mark and a contact pad, the first opening is formed over the alignment mark, and the second opening is formed over the contact pad.