IP Library › Granted Patent US 7,479,401
Granted Patent B2
US 7,479,401 · App. 11/414,128 · Granted Jan 20, 2009

Front side illuminated photodiode with backside bump

Assignee: Microsemi Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,479,401
App. No.
11/414,128
Filed
Apr 28, 2006
Granted
Jan 20, 2009
Kind
B2
Examiner
PHAM, HOAI V
Art Unit
2892
USPC
438/57
Abstract

This invention relates to a novel optoelectronic chip with one or more optoelectronic devices, such as photodiodes, fabricated on a front side of a semiconductor wafer and contacts on a backside of the semiconductor wafer. The backside contacts can be contact bumps, which allow the optoelectronic chip to achieve the benefits of flip chip packaging without flipping the optoelectronic chip upside down with respect to a chip carrier. In an optical communication system, a photodiode chip can be backside bumped to a chip carrier or an electronic chip, allowing front side illumination of the photodiode chip. Front side illumination offers many benefits, including improved fiber alignment, reduced manufacturing time, and overall cost reduction.

Claims (32)

1. A method of fabricating a front side illuminated photodiode with backside bump, the method comprising:

forming the photodiode on a front side of a semiconductor wafer;

forming first contacts on the front side, wherein the first contacts are respectively electrically coupled to a cathode and an anode of the photodiode; and

mounting the semiconductor wafer with the photodiode upside down on a support carrier before forming electrically conductive via holes through the semiconductor wafer and second contacts on a backside of the semiconductor wafer, wherein the second contacts are electrically coupled to the first contacts by the respective via holes.

2. The method of claim 1 , wherein the photodiode is a PIN photodiode fabricated using InP and an InGaAs layer is interposed between a P+ layer and a metal contact electrically coupled to the P+ layer.

3. The method of claim 1 , wherein the photodiode is a PIN photodiode and is formed by the following steps:

growing epitaxially N+, intrinsic and P+ layers on the front side of the semiconductor wafer;

applying one or more masks to form a desired structure for the PIN diode; and

depositing silicon nitride to exposed surfaces to reduce light reflection.

4. The method of claim 1 , wherein a metal contact on top of the photodiode has a shape with an interior area that defines an optical aperture for receiving a light signal.

5. The method of claim 4 , wherein the metal contact is a circular strip with a small opening on one side.

6. The method of claim 4 , wherein width and length dimensions of the photodiode are determined by a periphery of the metal contact on top of the photodiode.

7. The method of claim 1 , wherein the support carrier is a piece of sapphire.

8. The method of claim 1 , furthering comprising thinning the backside of the semiconductor wafer before forming the via holes.

9. The method of claim 1 , wherein infrared imaging alignment is used to align the via holes with the respective first contacts.

10. The method of claim 1 , further comprising applying a layer of dielectric material to the backside of the semiconductor wafer.

11. A method of fabricating an opto electronic device, the method comprising:

forming an optoelectronic device on a front side of a semiconductor wafer;

forming at least one electrical contact on the front side of the semiconductor wafer, wherein the electrical contact on the front side is electrically coupled to the optoelectronic device; and

mounting the semiconductor wafer with the optoelectronic device upside down on a support carrier before forming at least one electrical contact on a backside of the semiconductor wafer.

12. The method of claim 11 , wherein the optoelectronic device is a photodiode comprising at least one InP layer and an InGaAs layer is formed between the InP layer and a metal contact electrically coupled to the InP layer.

13. The method of claim 11 , further comprising a wrap-around conductor that electrically couples the electrical contact on the backside of the semiconductor wafer to the electrical contact on the front side of the semiconductor wafer.

14. The method of claim 11 , further comprising a via through the semiconductor wafer that electrically couples the electrical contact on the front side to the electrical contact on the backside of the semiconductor wafer.

15. The method of claim 11 , wherein the support carrier is a piece of sapphire.

16. A method of fabricating an array of optoelectronic devices, the method comprising:

forming an array of optoelectronic devices on a front side of a semiconductor wafer;

forming an array of first contacts on the front side of the semiconductor wafer, wherein the first contacts are electrically coupled to the respective optoelectronic devices; and

mounting the semiconductor wafer upside down on a support carrier before forming an array of vias through the semiconductor wafer and an array of second contacts on a backside of the semiconductor wafer, wherein the array of vias electrically couple the array of second contacts to the array of first contacts.

17. The method of claim 16 , wherein at least one of the optoelectronic devices is a PIN photodiode fabricated using InP material and an InGaAs layer is formed on a P+ layer of the PIN photodiode for making an ohmic contact.

18. The method of claim 16 , further comprising connecting the array of first contacts to a tester using a probe card for photonic testing at the wafer level.

19. The method of claim 16 , wherein the support carrier comprises sapphire and dual imaging alignment is used to align the array of vias with the array of first contacts.

20. The method of claim 16 , further comprising applying a layer of BCB to the backside and a layer of BCB to the first side of the semiconductor wafer with subsequent etching to expose the first contacts and the second contacts.

Assignments (17)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
NOTICE OF SUCCESSION OF AGENCY Recorded Apr 9, 2015
From: ROYAL BANK OF CANADA (AS SUCCESSOR TO MORGAN STANLEY & CO. LLC)
To: BANK OF AMERICA, N.A., AS SUCCESSOR AGENT
Reel/Frame 035657/0223 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2011
From: WHITE ELECTRONIC DESIGNS CORP.; ACTEL CORPORATION; MICROSEMI CORPORATION
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 025783/0613 →
Continuity (3)
Division 1066908100 · Sep 23, 2003
Provisional Application 6041342700 · Sep 25, 2002
Related Publication 20070105265A1 · May 10, 2007