Confined phase change memory with double air gap
A method is presented for reducing heat loss to adjacent semiconductor structures. The method includes forming a plurality of conductive lines within an interlayer dielectric, forming a barrier layer over at least one conductive line of the plurality of conductive lines, forming a via extending to a top surface of the barrier layer, and defining dual air gaps within the via and over the barrier layer.
1. A method for reducing heat loss to adjacent semiconductor structures, the method comprising:
forming a plurality of conductive lines within an interlayer dielectric;
forming a barrier layer over at least one conductive line of the plurality of conductive lines;
forming a via extending to a top surface of the barrier layer; and
defining dual air gaps within the via and over the barrier layer, the dual airgaps separated by phase change material layers.
2. The method of claim 1 , further comprising forming sacrificial layers adjacent sidewalls of the via.
3. The method of claim 2 , further comprising forming spacers adjacent sidewalls of the sacrificial layers.
4. The method of claim 3 , further comprising forming dielectric liners adjacent to the spacers.
5. The method of claim 4 , wherein the phase change material layers are Ge—Sb—Te (germanium-antimony-tellurium or GST) alloy layers.
6. The method of claim 5 , further comprising forming a dielectric between the GST alloy layers to define a first air gap of the dual air gaps.
7. The method of claim 6 , further comprising removing the sacrificial layers adjacent sidewalls of the via to define a second air gap of the dual air gaps.
8. The method of claim 7 , further comprising forming an electrode over the dual air gaps.
9. The method of claim 8 , wherein the second air gap occupies more space than the first air gap.
10. A method for reducing heat loss to adjacent semiconductor structures, the method comprising:
forming a barrier layer over at least one conductive line of a plurality of conductive lines;
forming a via to the first barrier layer;
defining a first air gap between Ge—Sb—Te (germanium-antimony-tellurium or GST) alloy layers; and
defining second air gaps on opposed ends of the first air gap.
11. The method of claim 10 , further comprising forming sacrificial layers adjacent sidewalls of the via.
12. The method of claim 11 , further comprising forming spacers adjacent sidewalls of the sacrificial layers.
13. The method of claim 12 , further comprising forming dielectric liners adjacent to the spacers.
14. The method of claim 13 , further comprising forming the GST alloy layers adjacent the dielectric liners.
15. The method of claim 14 , further comprising forming a dielectric between the GST alloy layers to define the first air gap.
16. The method of claim 15 , further comprising removing the sacrificial layers adjacent sidewalls of the via to define the second air gaps.
17. The method of claim 16 , further comprising forming an electrode over the first and second air gaps.
18. A semiconductor structure for reducing heat loss to adjacent semiconductor devices, the semiconductor structure comprising:
a plurality of conductive lines disposed within an interlayer dielectric;
a barrier layer disposed over at least one conductive line of the plurality of conductive lines;
a first air gap defined within a dielectric; and
second air gaps defined on opposed ends of the first air gap, the second air gaps separated by phase change material layers.
19. The semiconductor structure of claim 18 , wherein the phase change material layers are Ge—Sb—Te (germanium-antimony-tellurium or GST) alloy layers.
20. The semiconductor structure of claim 19 , wherein an electrode is disposed over the first and second air gaps.