Nonvolatile latch circuit and logic circuit, and semiconductor device using the same
To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.
1. A circuit comprising:
a first portion comprising a first logic gate and a second logic gate, wherein an output of the first logic gate is electrically connected to an input of the second logic gate and an output of the second logic gate is electrically connected to an input of the first logic gate; and
a second portion for holding data of the first portion, the second portion comprising:
a first switch electrically connected to the input of the first logic gate and the output of the second logic gate of the first portion through a first wiring;
a second switch electrically connected to a first terminal of the first switch, the output of the first logic gate, and the input of the second logic gate; and
a capacitor, a first electrode of the capacitor electrically connected to the first terminal of the first switch and a first terminal of the second switch, wherein the second switch includes an oxide semiconductor layer.
2. The circuit according to claim 1 , wherein the second portion further comprises an inverter electrically connected to the first switch, the second switch, and the capacitor.
3. The circuit according to claim 1 ,
wherein a second terminal of the first switch is electrically connected to the first wiring.
4. The circuit according to claim 1 , wherein a second terminal of the second switch is electrically connected to the output of the first logic gate and the input of the second logic gate through a second wiring.
5. The circuit according to claim 1 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.
6. The circuit according to claim 1 , wherein the first logic gate is a first inverter, and the second logic gate is a second inverter.
7. A semiconductor device comprising the circuit according to claim 1 and a display.
8. A circuit comprising:
a first portion comprising a first logic gate and a second logic gate, wherein an output of the first logic gate is electrically connected to an input of the second logic gate and an output of the second logic gate is electrically connected to an input of the first logic gate; and
a second portion for holding data of the first portion, the second portion comprising:
a switch electrically connected to the input of the first logic gate and the output of the second logic gate of the first portion through a first wiring;
a transistor electrically connected to a first terminal of the switch, the output of the first logic gate, and the input of the second logic gate; and
a capacitor, a first electrode of the capacitor electrically connected to the first terminal of the switch and one of a source and a drain of the transistor,
wherein a channel formation region of the transistor includes an oxide semiconductor layer.
9. The circuit according to claim 8 , wherein the second portion further comprises an inverter electrically connected to the switch, the transistor, and the capacitor.
10. The circuit according to claim 8 , wherein the transistor is configured to hold the data in the capacitor.
11. The circuit according to claim 8 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.
12. The circuit according to claim 8 , wherein the first logic gate is a first inverter, and the second logic gate is a second inverter.
13. The circuit according to claim 8 , wherein an off-current per 1 μm of a channel width of the transistor is less than or equal to 1×10 −17 A.
14. The circuit according to claim 8 ,
wherein the other of the source and the drain of the transistor is electrically connected to the output of the first logic gate and the input of the second logic gate through a second wiring.
15. A circuit comprising:
a first portion comprising a first logic gate and a second logic gate, wherein an output of the first logic gate is electrically connected to an input of the second logic gate and an output of the second logic gate is electrically connected to an input of the first logic gate; and
a second portion for holding data of the first portion, the second portion comprising:
a first transistor electrically connected to the input of the first logic gate and the output of the second logic gate of the first portion through a first wiring;
a second transistor electrically connected to one of a source and a drain of the first transistor, the output of the first logic gate, and the input of the second logic gate; and
a capacitor, a first electrode of the capacitor electrically connected to the one of the source and the drain of the first transistor and one of a source and a drain of the second transistor,
wherein a channel formation region of the second transistor includes an oxide semiconductor layer.
16. The circuit according to claim 15 , wherein the second portion further comprises an inverter electrically connected to the first transistor, the second transistor, and the capacitor.
17. The circuit according to claim 15 , wherein the second transistor is configured to hold the data in the capacitor.
18. The circuit according to claim 15 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.
19. The circuit according to claim 15 , wherein the first logic gate is a first inverter, and the second logic gate is a second inverter.
20. The circuit according to claim 15 ,
wherein the other of the source and the drain of the second transistor is electrically connected to the output of the first logic gate and the input of the second logic gate through a second wiring.