IP Library › Granted Patent US 10,510,669
Granted Patent B2
US 10,510,669 · App. 15/876,080 · Granted Dec 17, 2019

Multi-chip package and method of providing die-to-die interconnects in same

Inventors: Henning Braunisch (Chandler, AZ); Chia-Pin Chiu (Tempe, AZ); Aleksandar Aleksov (Chandler, AZ); Hinmeng Au (Phoenix, AZ); Stefanie M. Lotz (Phoenix, AZ); Johanna M. Swan (Scottsdale, AZ); Sujit Sharan (Chandler, AZ)
Assignee: Intel Corporation
H01L23/5385H01L23/13H01L23/5381H01L24/14H01L24/73H01L25/0652H01L25/0655H01L25/0657H01L21/6835H01L24/17H01L24/45H01L24/48H01L24/49H01L24/81H01L2224/0401H01L2224/13099H01L2224/141H01L2224/1403H01L2224/16145H01L2224/16225H01L2224/17181H01L2224/32245H01L2224/45099H01L2224/45147H01L2224/48091H01L2224/48227H01L2224/49175H01L2224/73207H01L2224/73253H01L2224/81001H01L2224/81005H01L2224/81801H01L2225/0651H01L2225/06513H01L2225/06517H01L2225/06562H01L2924/00011H01L2924/00014H01L2924/014H01L2924/01005H01L2924/01006H01L2924/01015H01L2924/01029H01L2924/01032H01L2924/01033H01L2924/01076H01L2924/01079H01L2924/10253H01L2924/10271H01L2924/10329H01L2924/12042H01L2924/1461H01L2924/15153H01L2924/19107H01L2924/351
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Quick Facts
Patent No.
US 10,510,669
App. No.
15/876,080
Granted
Dec 17, 2019
Kind
B2
Abstract

A multi-chip package includes a substrate ( 110 ) having a first side ( 111 ), an opposing second side ( 112 ), and a third side ( 213 ) that extends from the first side to the second side, a first die ( 120 ) attached to the first side of the substrate and a second die ( 130 ) attached to the first side of the substrate, and a bridge ( 140 ) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity ( 615, 915 ) in the substrate or between the substrate and a die layer ( 750 ). The bridge may constitute an active die and may be attached to the substrate using wirebonds ( 241, 841, 1141, 1541 ).

Claims (11)

1. A multi-chip package comprising:

a substrate having a first side, an opposing second side, and a third side that extends from the first side to the second side, the third side constituting a portion of an outside perimeter of the substrate;

a first die attached to the first side of the substrate and a second die attached to the first side of the substrate;

a bridge within an opening of the substrate, the bridge attached to the first die and to the second die, wherein the bridge creates a connection between the first die and the second die; and

one or more wire bonds coupling the bridge die to the substrate.

2. The multi-chip package of claim 1 , wherein the bridge comprises silicon.

3. The multi-chip package of claim 1 , wherein the opening of the substrate completely laterally surrounds the bridge.

4. The multi-chip package of claim 1 , wherein the bridge has an exposed backside opposite the first die and the second die.

5. The multi-chip package of claim 1 , wherein portions of the first die and second die overhanging the bridge have interconnect structures a smaller pitch than interconnect structures of portions of the first die and second die not overhanging the bridge.

6. The multi-chip package of claim 1 , wherein the first die and the second die are flip chip or controlled collapse attached to the bridge.

7. The multi-chip package of claim 1 , wherein the bridge does not include a through silicon via.

Continuity (3)
Division 13531827 · Jun 25, 2012
Division 12459007 · Jun 24, 2009
Related Publication 20180145031A1 · May 24, 2018
Cited By (4)
US 12,355,000 US 12,469,811 US 12,564,064 US 12,656,390