Pad structure and manufacturing method thereof in semiconductor device

1. A method of manufacturing a semiconductor device, comprising:

forming a memory cell on a substrate;

forming a conductive pad region to electrically couple to the memory cell;

depositing a dielectric layer over the conductive pad region;

forming a first passivation layer over the dielectric layer;

etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region;

forming a second passivation layer over the first passivation layer and the exposed first area of the conductive pad region; and

etching the second passivation layer to expose a second area of the conductive pad region.

2. The method according to claim 1 , wherein etching the second passivation layer to expose a second area of the conductive pad region comprises etching the second passivation layer using a self-aligned scheme.

3. The method according to claim 1 , wherein etching the first passivation layer through the dielectric layer comprises exposing a sidewall of the dielectric layer, and wherein forming a second passivation layer over the first passivation layer comprises forming the second passivation layer covering the sidewall of the dielectric layer.

4. The method according to claim 3 , wherein etching the second passivation layer to expose a second area of the conductive pad region comprises etching a portion of the first passivation layer.

5. The method according to claim 4 , wherein etching a portion of the first passivation layer comprises forming a dimple on a surface of the etched first passivation layer contacting the etched second passivation layer.

6. The method according to claim 1 , wherein etching the second passivation layer to expose a second area of the conductive pad region comprises exposing a horizontal portion of the first passivation layer.

7. The method according to claim 1 , wherein etching the second passivation layer to expose a second area of the conductive pad region comprises forming a rounded corner at a top portion of the second passivation layer.

8. The method according to claim 1 , wherein depositing a dielectric layer over the conductive pad region comprises forming a first oxide layer using a plasma-enhanced chemical vapor deposition over the conductive pad region and depositing a high-density plasma oxide over the first oxide layer.

9. The method according to claim 1 , wherein etching the second passivation layer to expose a second area of the conductive pad region comprises recessing a depth of the conductive pad region.

10. The method according to claim 1 , further comprising performing a thermal treatment subsequent to forming the second passivation layer.

11. A method of manufacturing a semiconductor device, comprising:

forming a memory cell on a substrate;

forming a conductive pad region to electrically couple to the memory cell;

depositing at least one dielectric layer over the conductive pad region;

forming a first passivation layer over the at least one dielectric layer;

forming a recess through the first passivation layer and the at least one dielectric layer, the recess exposing a first area of the conductive pad region; and

forming a second passivation layer over the conductive pad region, the second passivation layer comprising a sidewall covering a sidewall of the at least one dielectric layer and exposing a second area of the conductive pad region less than the first area.

12. The method according to claim 11 , wherein forming a second passivation layer over the conductive pad region comprises forming the second passivation layer to cover a horizontal portion and a sidewall of the first passivation layer.

13. The method according to claim 11 , further comprising forming a redistribution layer over the memory cell, wherein the conductive pad region is formed in a topmost layer of the redistribution layer.

14. The method according to claim 11 , further comprising forming a protection region covering the conductive pad region prior to depositing the at least one dielectric layer.

15. The method according to claim 11 , further comprising forming a conductive plug over the conductive pad region and laterally surrounded by the sidewall of the second passivation layer.

16. A method of manufacturing a semiconductor device, comprising:

forming a memory cell on a substrate;

constructing a redistribution layer over the memory cell, the constructing comprising;

forming metal line layers and metal via layers alternately over the memory cell;

forming a pad region at a topmost layer of the redistribution layer to electrically couple to the memory cell through the metal line layers and the metal via layers;

depositing a dielectric layer stack to cover the pad region;

depositing a first passivation layer over the dielectric layer stack;

forming a recess through the first passivation layer and the dielectric layer stack to thereby expose a first portion of the pad region;

depositing a second passivation layer over the recess, the first passivation layer and the exposed pad region;

etching a portion of the second passivation layer to expose a second portion of the pad region, the second portion comprising a width less than a width of the first portion; and

forming a conductive plug to electrically couple to the pad region.

17. The method according to claim 16 , wherein the second portion overlaps the first portion.

18. The method according to claim 16 , wherein forming a dielectric layer stack to cover the pad region comprising depositing a first oxide layer, a second oxide layer and a third oxide layer one over another using chemical vapor deposition, wherein the first oxide layer and the third oxide layer comprise a same material.

19. The method according to claim 16 , further comprising forming a protection region to cover a top portion of the pad region while exposing a sidewall of the pad region prior to forming the dielectric layer stack.

20. The method according to claim 16 , wherein forming a conductive plug to electrically couple to the pad region comprises forming the conductive plug to cover a portion of the second passivation layer.