Self-aligned di-silicon silicide bit line and source line landing pads in 3D vertical channel memory

1. A method for manufacturing a memory device, comprising:

forming an initial silicide layer, including depositing and annealing a precursor metal over a layer of silicon material on a top surface of a stack of conductive strips in amounts effective to result in a majority of the initial silicide layer being a mono-silicon silicide of the precursor metal; and

depositing and annealing additional silicon material over the initial silicide layer in amounts effective to result in formation of di-silicon silicide of the precursor metal to form a landing pad on the top surface of the stack of conductive strips, the formation of the di-silicon silicide of the precursor metal consuming mono-silicon silicide of the initial silicide layer so a majority of a silicide of the landing pad is di-silicon silicide.

2. The method of claim 1 , wherein forming the initial silicide layer includes annealing at a first temperature range, and the annealing of the additional silicon material is performed at a second temperature range higher than the first temperature range.

3. The method of claim 1 , comprising:

forming data storage structures on sidewalls of the conductive strips in the stack;

forming the layer of silicon material on the top surface of the stack of conductive strips and sidewalls of the conductive strips in the stack of conductive strips, the conductive strips in the stack including word lines coupled to memory cells on the sidewalls of the conductive strips in the stack, the layer of silicon material including a vertical thin channel film in the memory cells disposed vertically in contact with the data storage structures on the sidewalls of the conductive strips in the stack,

wherein the di-silicon silicide of the precursor metal of the landing pad is electrically continuous with and physically in contact with the vertical thin channel film on the sidewalls of the conductive strips in the stack,

wherein the memory cells have channels in the vertical thin channel film and gates in the conductive strips in the stack.

4. The method of claim 3 , said forming the layer of silicon material comprising:

depositing a first layer of silicon material conformally to a memory layer on the top surface of the stack of conductive strips and sidewalls of the conductive strips in the stack; and

depositing a second layer of silicon material non-conformally over the first layer of silicon material.

5. The method of claim 1 , comprising:

Removing remnants of the precursor metal, after said forming the initial silicide layer.

6. The method of claim 1 , comprising:

removing remnants of the additional silicon material, after the formation of the di-silicon silicide of the precursor metal.

7. The method of claim 1 , comprising:

forming a bit line over the landing pad, the bit line contacting the di-silicon silicide of the precursor metal of the landing pad.

8. The method of claim 1 , the memory device comprising a second landing pad disposed on a top surface of a second stack of conductive strips adjacent the first-mentioned stack of conductive strips, a majority of a silicide of the second landing pad being di-silicon silicide, the method comprising:

forming a source line over the second landing pad, the source line contacting the di-silicon silicide of the precursor metal of the second landing pad.

9. The method of claim 1 , wherein the precursor metal includes Cobalt.

10. The method of claim 1 , wherein the precursor metal includes Nickel.

11. A memory device including a plurality of memory cells, comprising:

a stack of conductive strips having sidewalls;

data storage structures on the sidewalls of the conductive strips in the stack;

a vertical thin channel film disposed vertically in contact with the data storage structures on the sidewalls of the conductive strips in the stack;

the memory cells in the plurality of memory cells having channels in the vertical thin channel film and gates in the conductive strips in the stack;

a landing pad including silicide disposed on a top surface of the stack of conductive strips,

wherein the landing pad including the silicide is electrically continuous with and physically in contact with the vertical thin channel film on the sidewalls of the conductive strips in the stack.

12. The memory device of claim 11 , the silicide consisting essentially of di-silicon silicide.

13. The memory device of claim 12 , wherein the di-silicon silicide of the landing pad includes CoSi 2 .

14. The memory device of claim 12 , wherein the di-silicon silicide of the landing pad includes NiSi 2 .

15. The memory device of claim 12 , comprising:

a bit line over the landing pad, the bit line contacting the di-silicon silicide of the landing pad.

16. The memory device of claim 12 , comprising:

a second landing pad disposed on a top surface of a second stack of conductive strips adjacent the first-mentioned stack of conductive strips, the second landing pad including the silicide consisting essentially of di-silicon silicide; and

a source line over the second landing pad, the source line contacting the di-silicon silicide of the second landing pad.

17. The memory device of claim 11 , wherein a majority of the silicide of the landing pad is di-silicon silicide.