Memory device and method for manufacturing the same
A memory device includes a substrate, a first conductive stripe disposed on the substrate and extending along a first direction, a second conductive stripe disposed on the first conductive stripe, a first pillar element and a spacer. The second conductive stripe extends along a second direction intersected with the first direction. A thickness of the second conductive stripe is greater than a thickness of the first conductive stripe, and the second conductive stripe is an integral structure. The first pillar element is disposed at an intersection between the first conductive stripe and the second conductive stripe, and extends from a top surface of the first conductive stripe to a bottom surface of the second conductive stripe along a third direction intersected with the first direction and the second direction. The first pillar element includes a switching layer and a memory layer corresponding to a first level.
1. A memory device, comprising:
a substrate;
a first conductive stripe disposed on the substrate and extending along a first direction;
a second conductive stripe disposed on the first conductive stripe and extending along a second direction, wherein the first direction and the second direction are parallel to an upper surface of the substrate, and the second direction is intersected with the first direction, a thickness of the second conductive stripe is greater than a thickness of the first conductive stripe, and the second conductive stripe is an integral structure;
a first pillar element disposed at an intersection between the first conductive stripe and the second conductive stripe, and extending from a top surface of the first conductive stripe to a bottom surface of the second conductive stripe along a third direction, wherein the third direction is intersected with the first direction and the second direction, wherein the first pillar element comprises a switching layer and a memory layer corresponding to a first level; and
a spacer surrounding and directly contacting the first pillar element,
wherein the second conductive stripe has a same width in the first direction, and the spacer further surrounds the second conductive stripe to have a same width in the first direction.
2. The memory device according to claim 1 , wherein a material of the spacer is silicon nitride.
3. The memory device according to claim 1 , wherein the spacer directly contacts the switching layer and the memory layer.
4. The memory device according to claim 1 , wherein the spacer has a single-layer structure.
5. The memory device according to claim 1 , wherein a material of the spacer includes nitride.
6. The memory device according to claim 1 , wherein a thickness of the spacer is between 2 nanometers and 5 nanometers.
7. The memory device according to claim 1 , wherein the first pillar element further comprises a first buffer layer, a second buffer layer, and a third buffer layer, the first buffer layer is disposed between the first conductive stripe and the switching layer, the second buffer layer is disposed between the switching layer and the memory layer, and the third buffer layer is disposed between the memory layer and the second conductive stripe.
8. The memory device according to claim 7 , wherein the first pillar element further comprises a first barrier layer and a second barrier layer, and the first barrier layer is disposed between the second buffer layer and the memory layer, the second barrier layer is disposed between the memory layer and the third buffer layer.
9. The memory device according to claim 1 , further comprising:
a third conductive stripe disposed on the second conductive stripe and extending along the first direction; and
a second pillar element disposed at an intersection between the second conductive stripe and the third conductive stripe, and extending from a top surface of the second conductive stripe to a bottom surface of the third conductive stripe along the third direction, wherein the second pillar element comprises a switching layer and a memory layer corresponding to a second level, and the second level is disposed above the first level.
10. The memory device according to claim 9 , wherein the second pillar element further comprises a first buffer layer, a second buffer layer and a third buffer layer in the second level, the first buffer layers in the second level is disposed between the second conductive stripe and the switching layer in the second level, and the second buffer layer in the second level is disposed between the switching layer in the second level and the memory layer in the second level, and the third buffer layer in the second level is disposed between the memory layer in the second level and the third conductive stripe.