IP Library › Granted Patent US 10,515,898
Granted Patent B2
US 10,515,898 · App. 15/978,443 · Granted Dec 24, 2019

Circuit board incorporating semiconductor IC and manufacturing method thereof

Inventors: Kazutoshi Tsuyutani (Tokyo, JP); Masashi Katsumata (Tokyo, JP)
Assignee: TDK CORPORATION
H01L23/5384H01L24/03H01L24/06H01L24/19H01L24/24H01L24/82H01L24/96H01L2224/04105H01L2224/24137H01L2224/24226H01L2224/32225H01L2224/73267H01L2224/82005H01L2224/9222H01L2224/96
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Quick Facts
Patent No.
US 10,515,898
App. No.
15/978,443
Granted
Dec 24, 2019
Kind
B2
Abstract

Disclosed herein is a circuit board that includes a first insulating layer having an upper surface; a first wiring layer embedded in the first insulating layer, the first wiring layer having an upper surface exposed from the upper surface of the first insulating layer such that the upper surface of the first wiring layer is substantially coplanar with the upper surface of the first insulating layer; a semiconductor IC mounted on the upper surface of the first wiring layer with a die attach material interposed therebetween; and a second insulating layer stacked on the upper surface of the first wiring layer so as to embed the semiconductor IC, wherein a bottom surface of the die attach material is in contact with both of the upper surface of the first insulating layer and the upper surface of the first wiring layer.

Claims (46)

1. A circuit board comprising:

a first insulating layer having a single layer structure and having an upper surface;

a first wiring layer embedded in the first insulating layer, the first wiring layer having an upper surface exposed from the upper surface of the first insulating layer such that the upper surface of the first wiring layer is substantially coplanar with the upper surface of the first insulating layer;

a semiconductor IC mounted on the upper surface of the first wiring layer with a die attach material interposed therebetween;

a second insulating layer stacked on the upper surface of the first wiring layer so as to embed the semiconductor IC;

a third wiring layer formed on a lower surface of the first insulating layer; and

a third through-hole conductor penetrating the first insulating layer to electrically connect the first wiring layer to the third wiring layer,

wherein a bottom surface of the die attach material is in contact with both of the upper surface of the first insulating layer and the upper surface of the first wiring layer.

2. The circuit board as claimed in claim 1 , wherein the bottom surface of the die attach material is in contact with a plurality of signal wires constituting the first wiring layer.

3. The circuit board as claimed in claim 1 , further comprising:

a second wiring layer formed on an upper surface of the second insulating layer;

a first through-hole conductor penetrating the second insulating layer to electrically connect the first wiring layer to the second wiring layer; and

a second through-hole conductor penetrating the second insulating layer to electrically connect the second wiring layer to a terminal electrode of the semiconductor IC.

4. The circuit board as claimed in claim 1 , further comprising:

a third insulating layer stacked on the upper surface of the second insulating layer so as to embed the second wiring layer;

a fourth wiring layer formed on an upper surface of the third insulating layer; and

a fourth through-hole conductor penetrating the third insulating layer to electrically connect the second wiring layer to the fourth wiring layer.

5. The circuit board as claimed in claim 1 , wherein the die attach material is a die attach film bonded on a bottom surface of the semiconductor IC.

6. The circuit board as claimed in claim 5 , wherein the die attach film is thicker than a silicon part constituting the semiconductor IC.

7. The circuit board as claimed in claim 1 , wherein the first insulating layer is free from a semiconductor IC.

8. The circuit board as claimed in claim 1 , wherein the third wiring layer is formed on the lower surface of the first insulating layer such that the third wiring layer protrudes from the lower surface of the first insulating layer.

9. A method of manufacturing a circuit board, the method comprising:

a first step for preparing a stacked body of a base and a conductor foil and mounting a semiconductor IC on the conductor foil with a die attach material interposed therebetween;

a second step for forming a second insulating layer on the conductor foil so as to embed the semiconductor IC;

a third step for removing the base;

a fourth step for patterning the conductor foil to form a first wiring layer; and

a fifth step for forming a first insulating layer on a lower surface of the second insulating layer so as to embed the first wiring layer,

wherein in the fourth step, the conductor foil is patterned so that a portion of a bottom surface of the die attach material is covered with the first wiring layer and a remaining portion of the bottom surface of the die attach material is exposed, thereby the remaining portion of the bottom surface of the die attach material is in contact with the first insulating layer, and

wherein the method further comprises a step for forming, after the second step, a first through hole that penetrates the second insulating layer to expose the conductor foil and a second through hole that penetrates the second insulating layer to expose a terminal electrode of the semiconductor IC.

10. The method of manufacturing a circuit board as claimed in claim 9 ,

wherein the conductor foil includes a first conductor foil and a second conductor foil that are stacked in this order on a surface of the base, and

wherein in the third step, the first conductor foil and the second conductor foil are peeled off at an interface therebetween, thereby using the second conductor foil as a material for the first wiring layer.

11. The method of manufacturing a circuit board as claimed in claim 10 , wherein the second conductor foil is thicker than the first conductor foil.

12. A circuit board comprising:

a first insulating layer having a single layer structure and having an upper surface;

a second insulating layer having a lower surface;

a first wiring layer embedded in the first insulating layer, the first wiring layer having an upper surface exposed from the upper surface of the first insulating layer;

a second wiring layer formed on a lower surface of the first insulating layer;

a through-hole conductor penetrating the first insulating layer to electrically connect the first wiring layer to the second wiring layer;

a semiconductor IC embedded in the second insulating layer; and

a die attach material provided between the first insulating layer and the semiconductor IC, the die attach material having a lower surface that is in contact with the upper surface of the first wiring layer,

wherein the upper surface of the first insulating layer, the upper surface of the first wiring layer, the lower surface of the second insulating layer, and the lower surface of the die attach material are substantially coplanar with one another.

13. The circuit board as claimed in claim 12 , wherein the first wiring layer includes a plurality of signal wires that are in contact with the lower surface of the die attach material.

14. The circuit board as claimed in claim 12 , wherein the die attach material comprises a die attach film thicker than the semiconductor IC.

15. The circuit board as claimed in claim 12 , wherein the first insulating layer is free from a semiconductor IC.

16. The circuit board as claimed in claim 12 , wherein the second wiring layer is formed on the lower surface of the first insulating layer such that the second wiring layer protrudes from the lower surface of the first insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2018
From: TSUYUTANI, KAZUTOSHI; KATSUMATA, MASASHI
To: TDK CORPORATION
Reel/Frame 045794/0608 →
Continuity (1)
Related Publication 20180337131A1 · Nov 22, 2018
Cited By (1)
US 12,733,547