Semiconductor device and fabrication thereof
A semiconductor device includes a first fin, a second fin, an isolation gate and a dielectric dummy gate. The first and second fins extend in a first direction. The isolation gate extends in a second direction and crosses the first fin. The isolation gate includes a conductive material. The dielectric dummy gate extends from one end of the isolation gate in the second direction and overlaps with the second fin.
1. A semiconductor device, comprising:
a first fin extending in a first direction;
a second fin extending in the first direction;
an isolation gate extending in a second direction and crossing the first fin, wherein the isolation gate comprises a conductive material; and
a dielectric dummy gate extending from one end of the isolation gate in the second direction and overlapping with the second fin.
2. The semiconductor device of claim 1 , wherein the isolation gate is electrically tied to a Vdd voltage source.
3. The semiconductor device of claim 1 , further comprising:
a third fin extending in the first direction and substantially aligned with the second fin, wherein the dielectric dummy gate is interposed between the second fin and the third fin.
4. The semiconductor device of claim 1 , wherein a bottom of the dielectric dummy gate is lower than a top surface of the second fin.
5. The semiconductor device of claim 1 , wherein a sidewall of the isolation gate is flush with a sidewall of the dielectric dummy gate.
6. The semiconductor device of claim 1 , further comprising:
a gate electrode extending in the second direction, wherein a length of the gate electrode in the second direction is substantially equal to a length of a combination of the isolation gate and the dielectric dummy gate in the second direction.
7. The semiconductor device of claim 1 , wherein a bottom of the dielectric dummy gate is lower than a bottom of the isolation gate.
8. The semiconductor device of claim 1 , further comprising:
a gate dielectric layer wrapping around the isolation gate; and
a spacer in contact with the gate dielectric layer and a sidewall of the dielectric dummy gate.
9. The semiconductor device of claim 8 , wherein a bottom of the spacer is higher than a bottom of the dielectric dummy gate.
10. The semiconductor device of claim 1 , wherein the first fin comprises germanium.
11. The semiconductor device of claim 1 , wherein the second fin comprises a non-germanium-containing semiconductor material.
12. A semiconductor device, comprising:
a first fin extending in a first direction;
a second fin extending in the first direction and substantially aligned with the first fin;
a dielectric dummy gate extending in a second direction and interposed between the first fin and the second fin;
a third fin extending in the first direction; and
an isolation gate extending in the second direction and crossing the third fin, wherein the isolation gate is substantially aligned with the dielectric dummy gate.
13. The semiconductor device of claim 12 , wherein the isolation gate abuts the dielectric dummy gate.
14. The semiconductor device of claim 12 , wherein the dielectric dummy gate has a first sidewall in contact with the first fin and a second sidewall in contact with the second fin.
15. The semiconductor device of claim 12 , further comprising:
a gate electrode crossing the third fin, wherein the gate electrode and the isolation gate comprise the same work function metal.
16. The semiconductor device of claim 12 , wherein a width of the isolation gate in the first direction is substantially equal to a width of the dielectric dummy gate in the first direction.
17. The semiconductor device of claim 12 , further comprising:
a semiconductor substrate having an N-type well region, wherein the isolation gate is over the N-type well region.
18. The semiconductor device of claim 12 , further comprising:
a semiconductor substrate having a P-type well region, wherein the dielectric dummy gate is over the P-type well region.
19. A method of manufacturing a semiconductor device, the method comprising:
forming a first fin over an N-type well region and a second fin over a P-type well region;
forming a gate across the first fin and the second fin;
etching a first portion of the gate to expose a portion of the second fin, wherein a second portion of the gate remains across the first fin;
etching the exposed portion of the second fin to break the second fin into a plurality of third fins; and
filling a space between the third fins with a dielectric material.
20. The method of claim 19 , further comprising:
replacing the second portion of the gate with a metal gate.