Granted Patent B2

US 12,230,633 · App. 18/362,764 · Granted Feb 18, 2025

Inventor: Jhon-Jhy Liaw (Hsinchu County, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

H01L27/0886H01L21/823431H01L27/0207H01L29/0692H01L29/66545H01L27/0924H01L27/1211H01L29/7853H01L29/7855H01L29/7856H10B12/056H10B12/36

Abstract

Claims (31)

1. An integrated circuit (IC) structure, comprising:

a first circuit comprising a first semiconductor fin, a first gate electrode extending across the first semiconductor fin, and a first gate dielectric layer spacing the first gate electrode apart from the first semiconductor fin;

a second circuit comprising a second semiconductor fin, a second gate electrode extending across the second semiconductor fin, and a second gate dielectric layer spacing the second gate electrode apart from the second semiconductor fin; and

a third circuit comprising a third semiconductor fin, a third gate electrode extending across the third semiconductor fin, and a third gate dielectric layer spacing the third gate electrode apart from the third semiconductor fin,

wherein the first gate dielectric layer has a thickness greater than a thickness of the second gate dielectric layer, and the third semiconductor fin has a width less than a width of the second semiconductor fin.

2. The IC structure of claim 1 , wherein the thickness of the first gate dielectric layer is greater than a thickness of the third gate dielectric layer.

3. The IC structure of claim 1 , wherein the width of the second semiconductor fin is greater than a width of the first semiconductor fin.

4. The IC structure of claim 1 , wherein the width of the third semiconductor fin is greater than a width of the first semiconductor fin.

5. The IC structure of claim 1 , wherein a ratio of the thickness of the first gate dielectric layer to the thickness of the second gate dielectric layer is greater than 1.3.

6. The IC structure of claim 1 , wherein a ratio of the width of the second semiconductor fin to a width of the first semiconductor fin is greater than 1.05.

7. The IC structure of claim 1 , wherein a ratio of the width of the second semiconductor fin to a width of the first semiconductor fin is greater than 1.1.

8. The IC structure of claim 1 , wherein the second circuit is a core circuit, and the first circuit is an I/O circuit having a higher operation voltage than the core circuit.

9. The IC structure of claim 1 , wherein the third circuit includes a static random access memory (SRAM) cell.

10. An IC structure, comprising:

a first circuit comprising a plurality of first semiconductor fins arranged at a first pitch, a first gate electrode extending across the plurality of first semiconductor fins, and a first gate dielectric layer between the first gate electrode and the plurality of first semiconductor fins; and

a second circuit comprising a plurality of second semiconductor fins arranged at a second pitch, a second gate electrode extending across the plurality of second semiconductor fins, and a second gate dielectric layer between the second gate electrode and the plurality of second semiconductor fins,

wherein the first gate dielectric layer has a thickness greater than a thickness of the second gate dielectric layer, one of the plurality of first semiconductor fins has a minimal width less than a minimal width of one of the plurality of second semiconductor fins, and the first pitch of the plurality of first semiconductor fins is equal to the second pitch of the plurality of second semiconductor fins.

11. The IC structure of claim 10 , wherein the first gate electrode has a first gate length measured along a lengthwise direction of the plurality of first semiconductor fins, the second gate electrode has a second gate length measured along a lengthwise direction of the plurality of second semiconductor fins, and a ratio of the first gate length to the second gate length is greater than 2.

12. The IC structure of claim 10 , wherein the first pitch of the plurality of first semiconductor fins is less than 32 nm.

13. The IC structure of claim 10 , wherein the plurality of first semiconductor fins comprises a plurality of silicon germanium fins and a plurality of silicon fins.

14. The IC structure of claim 10 , wherein the plurality of second semiconductor fins comprises a plurality of silicon germanium fins and a plurality of silicon fins.

15. An IC structure comprising:

a first circuit comprising a first semiconductor fin, a first gate electrode extending across the first semiconductor fin, and a first gate dielectric layer spacing the first gate electrode apart from the first semiconductor fin;

a second circuit comprising a second semiconductor fin, a second gate electrode extending across the second semiconductor fin, and a second gate dielectric layer spacing the second gate electrode apart from the second semiconductor fin; and

a third circuit comprising a third semiconductor fin, a third gate electrode extending across the third semiconductor fin, and a third gate dielectric layer spacing the third gate electrode apart from the third semiconductor fin,

wherein the first gate dielectric layer has a thickness greater than a thickness of the second gate dielectric layer and a thickness of the third gate dielectric layer, and the third semiconductor fin has a width less than a width of the second semiconductor fin.

16. The IC structure of claim 15 , wherein the first circuit is an I/O circuit.

17. The IC structure of claim 16 , wherein the second and third circuits are not I/O circuits.

18. The IC structure of claim 15 , wherein the width of the second semiconductor fin is greater than a width of the first semiconductor fin.

19. The IC structure of claim 15 , wherein the width of the third semiconductor fin is greater than a width of the first semiconductor fin.

20. The IC structure of claim 15 , wherein a ratio of the thickness of the first gate dielectric layer to the thickness of the second gate dielectric layer is greater than 1.3.

Assignments (1)

Continuity (4)

References Cited (71)