Semiconductor device
A semiconductor device includes a semiconductor substrate, a gate structure, an isolation structure, and a source/drain region. The semiconductor substrate includes a fin. The gate structure is disposed on the fin and is disposed straddling the fin. The isolation structure covers a sidewall and a top surface of the fin. The source/drain region is disposed in the fin and extends beyond the top surface of the fin.
1. A semiconductor device, comprising:
a semiconductor substrate, wherein the semiconductor substrate comprises a fin;
a gate structure disposed on the fin and disposed straddling the fin;
an isolation structure covering a sidewall and a top surface of the fin; and
a source/drain region disposed in the fin and extending beyond the top surface of the fin.
2. The semiconductor device according to claim 1 , wherein the source/drain region is disposed between the gate structure and the isolation structure.
3. The semiconductor device according to claim 1 , further comprising:
a first spacer disposed on a sidewall of the gate structure and disposed on the fin; and
a second spacer disposed on a sidewall of the isolation structure and disposed on the top surface of the fin.
4. The semiconductor device according to claim 3 , wherein the source/drain region is disposed between the first spacer and the second spacer.
5. The semiconductor device according to claim 3 , wherein the first spacer and the second spacer are separated from each other.
6. The semiconductor device according to claim 3 , wherein a material of the first spacer is identical to a material of the second spacer.
7. The semiconductor device according to claim 3 , further comprising:
a liner disposed on the top surface of the fin and disposed between the isolation structure and the fin.
8. The semiconductor device according to claim 7 , wherein the second spacer is further disposed on a sidewall of the liner.
9. The semiconductor device according to claim 1 , wherein a top surface of the gate structure is higher than a top surface of the isolation structure.
10. The semiconductor device according to claim 1 , further comprising:
an interlayer dielectric covering the source/drain region and a top surface of the isolation structure, wherein a top surface of the gate structure is not covered by the interlayer dielectric.
11. The semiconductor device according to claim 10 , wherein a part of the interlayer dielectric is disposed between the gate structure and the isolation structure and disposed above the source/drain region.
12. The semiconductor device according to claim 1 , wherein the gate structure and the isolation structure are elongated in the same direction.
13. The semiconductor device according to claim 1 , wherein the isolation structure is elongated in a direction orthogonal to a direction where the fin is elongated.
14. The semiconductor device according to claim 1 , wherein the isolation structure comprises a T-shaped structure in a cross-sectional view of the semiconductor device.