Electronic device including a tunnel layer
An electronic device includes a semiconductor layer, a tunneling layer formed of a material including a two-dimensional (2D) material so as to directly contact a certain region of the semiconductor layer, and a metal layer formed on the tunneling layer.
1. A transistor comprising:
a semiconductor layer including a channel region;
first and second tunneling layers including a two-dimensional (2D) material and formed on the semiconductor layer so as to be separated from each other and directly contact, certain regions of the semiconductor layer;
a source electrode and a drain electrode as metal electrodes respectively formed on the first and second tunneling layers and in direct contact with the first and second tunneling layers, respectively;
a gate electrode facing the channel region; and
the semiconductor layer, only in certain regions, directly contacting the first and second tunneling layers and having a doping density that is 10 19 cm −3 or less.
2. The transistor of claim 1 , wherein the first and second tunneling layers are formed of the 2D material so as to pass electrons therethrough.
3. The transistor of claim 1 , wherein the first and second tunneling layers are formed of a 2D laminated transition metal chalcogenide nanosheet.
4. The transistor of claim 1 , with wherein the first and second tunneling layers each independently comprises at least one layer of a plate-shaped structure material including a combination of at least one of titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), technetium (Tc), rhenium (Re), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), and platinum (Pt), and at least one of sulfur (S), selenium (Sc), and tellurium (Te).
5. The transistor of claim 1 , wherein the first and second tunneling layers each independently comprises at least one layer of a plate-shaped structure material including a hexagonal boron nitride (h-BN) or comprises a dopant configured to change a Fermi level of a plate-shaped structure material.
6. The transistor of claim 1 , further comprising a gate insulating layer located between the channel region and the gate electrode.
7. The transistor of claim 1 , wherein the semiconductor layer comprises a semiconductor substrate.
8. The transistor of claim 1 , wherein the semiconductor layer comprises at least one of silicon, germanium, silicon-germanium, II-VI group semiconductors, and III-V group semiconductors.