IP Library Granted Patent US 10,528,487
Granted Patent B2
US 10,528,487 · App. 15/806,440 · Granted Jan 7, 2020

Computer system software/firmware and a processor unit with a security module

Inventors: Angel Nunez Mencias (Stuttgart, DE); Jakob C. Lang (Weil im Schoenbuch, DE); Martin Recktenwald (Schoenaich, DE); Ulrich Mayer (Weil im Schoenbuch, DE)
Assignee: International Business Machines Corporation
G06F12/1408G06F13/24G06F2212/1052
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,528,487
App. No.
15/806,440
Granted
Jan 7, 2020
Kind
B2
Abstract

Technology for decrypting and using a security module in a processor cache in a secure mode such that dynamic address translation prevents access to portions of the volatile memory outside of a secret store in a volatile memory.

Claims (27)

1. A computer implemented method for use with a security module including program instructions for providing a secret store in a volatile memory for secret data and an interface for interacting with an operating system, the method comprising:

storing, in a processor cache included in a processor, data constituting the security module in an encrypted form that can be decrypted by a secret key;

switching the processor to a secure mode;

responsive to the switching to the secure mode, disabling a write operation, with the write operation being an operation that writes the data constituting the security module from the processor cache to a volatile memory;

decrypting, in the processor cache, the data constituting the security module with the secret key;

configuring dynamic address translation to prevent access to portions of the volatile memory outside of the secret store;

receiving data through the interface of the security module;

encrypting, by the security module and in the processor cache, the data received through the interface of the security module using a public key;

enabling the write operation; and

switching the processor to a normal operating system mode;

wherein the processor cache included in the processor includes:

a first level instruction cache included in the processor;

a first level data cache included in the processor;

a second level instruction cache included in the processor; and

a second level data cache included in the processor.

2. The method of claim 1 further comprising:

disabling the write operation for data tagged with a non-secure flag.

3. The method of claim 1 wherein the interface of the security module is in the form of an application programming interface using a crypto architecture.

4. The method of claim 1 further comprising:

receiving, by the processor, an interrupt request;

responsive to the interrupt request, suspending execution of the security module; and

subsequent to the encryption of the security module, passing control to an interrupt handling program.

5. The method of claim 4 further comprising:

terminating the interrupt request; and

responsive to the termination of the interrupt request, restarting the security module.

6. The method of claim 1 further comprising:

sharing the security module between a plurality of programs using a semaphore mechanism to serialize access to the secret store of the volatile memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2017
From: NUNEZ MENCIAS, ANGEL; LANG, JAKOB C.; RECKTENWALD, MARTIN; MAYER, ULRICH
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044069/0237 →
Continuity (2)
Continuation 15658441 · Jul 25, 2017
Related Publication 20190034357A1 · Jan 31, 2019